datasheet. Catalyst Semiconductor, datasheet. Datasheet - Page 3

• Manufacturer Part Number: datasheet.
• Description: CAT24WC32
• Manufacturer: Catalyst Semiconductor

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
CC
PUR
F
T
t
t
t
t
t
t
t
t
t
t
t
t
t
= 1.8 V to 5.5 V, unless otherwise specified.
t
PUW
AA
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
DH
PUR
t
SCL
I
(1)
(1)
(1)
WR
and t
(1)
PUW
are the delays required from the time V
Power-up to Read Operation
Power-up to Write Operation
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
CC
is stable until the specified operation can be initiated.
3
250
100
4.7
4.7
4.7
0
4
4
0
4
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
100
100
300
3.5
1
100
100
1.3
0.6
1.3
0.6
0.6
0.6
0
0
400
300
100
0.9
0.3
1
1
5
Doc No. 1073, Rev. D
kHz
ms
ms
ms
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns