datasheet. Catalyst Semiconductor, datasheet. Datasheet - Page 6
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datasheet.
Manufacturer Part Number
datasheet.
Description
CAT24WC32
Manufacturer
Catalyst Semiconductor
Datasheet
1.DATASHEET..pdf
(10 pages)
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC01. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC01 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
The CAT24FC01 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC01 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Doc. No. 1073, Rev. D
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
SDA LINE
MASTER
S
R
S
T
A
T
ADDRESS
SLAVE
S
S
T
A
R
T
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
ADDRESS
SLAVE
A
C
K
ADDRESS (n)
BYTE
C
A
K
ADDRESS
BYTE
C
A
K
6
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC01 in a single write cycle.
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24FC01 initiates the internal write cycle. ACK
polling can be initiated immediately.
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC01 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC01 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
The CAT24FC01 is designed with a hardware protect
pin that enables the user to protect the entire memory.
Thehardware protection feature of the CAT24FC01 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC01 allows the user to protect against inadvertent
programming of the memory array. If the WP pin is tied
to Vcc, the entire memory array is protected and becomes
read only. The entire memory becomes write protected
regardless of whether the write protect register has been
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
DATA n
A
C
K
DATA
A
C
K
DATA n+1
A
C
K
P
S
O
P
T
A
C
K
DATA n+7
This involves
C
A
K
O
S
T
P
P