AD1986 Analog Devices, AD1986 Datasheet - Page 25

• Manufacturer Part Number: AD1986
• Manufacturer: Analog Devices

Preliminary Technical Data
GENERAL-PURPOSE (REGISTER 0x20)
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
Reg
0x20
Table 44.
Register
LPBK
(Loop-
Back
Control)
MS
(MIC
Select)
MIX
(Mono
Output
Select)
DRSS [1:0]
(Double
Rate Slot
Select)
x
AUDIO INT AND PAGING (REGISTER 0x24)
This register controls the audio interrupt and register paging mechanisms.
Reg
0x24
Table 45.
Register
PG [3:0]
(Page Selector
(Read/Write))
I0
(Interrupt Enable
(Read/Write))
Name
General-
Purpose
Name
Audio Int and
Paging
Function
This bit enables the digital internal loop back from the ADC to the front DAC. This feature is normally used for
testing and troubleshooting. See LBKS bit in Register 0x74 for changing the loop back path to use the
SURROUND or CENTER/LFE DACs.
Used in conjunction with the OMS [2:0] (0x74 D10:08]), 2CMIC (0x76 D06) and MMIX (0x7A D02). Selects which
MIC input goes into the ADC0 record selector’s MIC channel inputs. When set, this bit swaps the left and right
channels. Selects mono output audio source.
MIX
0
1
The DRSS bits specify the slots for the n+1 sample outputs. PCM L (n+1) and PCM R (n+1) data are by default
provided in output Slots 10 and 11.
DRSS [1:0]
Reserved.
Function
This register is used to select a descriptor of 16 word pages between Registers 0x60 to 0x6F. A value of 0x0 is used to
select vendor specific space to maintain compatibility with AC ’97 Revision 2.2 vendor specific registers. System
software can determine implemented pages by writing the page number and reading the value back. If the value read
back does not match the value written, the page is not implemented. All implemented pages must be in consecutive
order (i.e. Page 0x2 cannot be implemented without Page 0x1).
PG [3:0]
000 (Page 0)
001 (Page 1)
Page 0xh–0xF
Software should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with
modem Slot 12—GPI functionality. AC ’97 Revision 2.2 compliant controllers will not likely support audio CODEC
interrupt infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for
sense cycle max delay (defined by software) to determine if an interrupting event has occurred.
I0
0
1
D15
x
D15
I4
D14
x
D14
I3
Mono Output Connection
MIX—Connected to the mono mixer output.
MIC—Connected to the left channel of the MIC selector and swap.
DRSS [1:0]
00
01
1x
D13
x
D13
I2
Page 0 (vendor) registers
Page ID 01, registers defined in AC ’97, Revision 2.3
Interrupt Mask Status
Interrupt generation is masked
Interrupt generation is unmasked
Addressing Page Selection
Reserved
D12
x
D12
I1
D11
DRSS1
D11
I0
D10
DRSS0
D10
x
Rev. 0 | Page 25 of 52
D9
x
D9
MIX
D8
x
D8
MS
D7
x
D7
LPBK
Function
PCM L, R (n+1) data is on Slots 10 and 11
PCM L, R (n+1) data is on Slots 7 and 8
Reserved
D6
x
x
D6
D5
x
D5
x
D4
x
x
D4
D3
PG3
x
D3
D2
PG2
D2
x
D1
PG1
D1
x
D0
PG0
x
D0
Default
Default
Default
AD1986
Default
Default:
disabled
(0x0)
Default
Default
Default: 0
Default
0x0000
Default
0xxx00