AD1986 Analog Devices, AD1986 Datasheet - Page 37

• Manufacturer Part Number: AD1986
• Manufacturer: Analog Devices

Preliminary Technical Data
REF
20
21
22
23
24
25
26
27
28
29
30
31
FMUTE = Output is forced to mute independent of the respective volume register setting.
ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.
OUT = Nothing is plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down action).
IN = Jack has plug inserted and therefore the JS status is 1 (via the CODEC JS pin internal pull-up).
SERIAL CONFIGURATION (REGISTER 0x74)
When Register 0x00 is written (soft reset) the SLOT 16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK bits do not reset. All bits are reset
on a hardware reset or power-on reset.
Reg
0x74
Table 62.
Register
SPLNK
(S/PDIF
LINK)
SPDZ
(S/PDIF
DACZ)
SPAL
(S/PDIF
ADC Loop
Around)
(CSWP
CENTER/LFE
Swap)
INTS
(Interrupt
Mode
Select)
Name
Serial
Configuration
JS1
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
OUT (0)
IN (1)
IN (1)
OUT (0)
OUT (0)
IN (1)
IN (1)
This bit selects the audio interrupt implementation path. Note that this bit does not generate an interrupt, rather it steers the
path of the generated interrupt.
Function
This bit enables the S/PDIF to link with the front DACs for data requesting. When linked the S/PDIF and front DACs should be
set to the same data rate as they both generate data requests at the front DAC’s request rate.
SPLNK
0
1
Sets data fill mode for S/PDIF transmitter FIFO under-runs. When this bit is set to ON (1) the S/PDIF and ADC rates should be
set to the same rate.
SPDZ
0
1
SPAL
0
1
Swaps the CENTER/LFE channels. Some systems have a swapped external connection for the CENTER and LFE channels.
Setting this bit will swap these channels internal to the CODEC. Note that the CENTER and LFE controls do not change and
remain at the same addresses and bit assignments.
CSWP
0
1
INTS
0
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
OUT (0)
IN (1)
JS0
D15
SLOT
16
JSMT2
1
1
1
1
1
1
1
1
1
1
1
1
D14
REGM2
D13
REGM1
JSMT1
0
0
0
0
1
1
1
1
1
1
1
1
Function
S/PDIF and front DACs are not linked
S/PDIF and front DACs are linked
On Under-Runs
Repeat last sample out the S/PDIF stream
Forces midscale sample out the S/PDIF stream
S/PDIF Transmitter Source
Connected to the AC-LINK stream
Connected to the digital ADC stream
CENTER Pin
CENTER channel
LFE channel
Interrupt Mode
Bit 0 SLOT 12 (modem interrupt)
D12
REGM0
1
1
1
1
0
0
0
0
1
1
1
1
JSMT0
D11
REGM3
HP
OUT
FMUTE
FMUTE
ACTIVE
ACTIVE
**
**
**
**
**
**
**
**
D10
OMS2
Rev. 0 | Page 37 of 52
LINE
OUT
FMUTE
FMUTE
ACTIVE
ACTIVE
**
**
**
**
**
**
**
**
D9
OMS1
D8
OM0
C/LFE
OUT
FMUTE
FMUTE
ACTIVE
ACTIVE
**
**
**
**
**
**
**
**
D7
SPOVR
LFE Pin
LFE channel
CENTER channel
D6
LBKS1
SURR
OUT
FMUTE
FMUTE
ACTIVE
ACTIVE
**
**
**
**
**
**
**
**
D5
LBKS0
MONO
OUT
ACTIVE
ACTIVE
FMUTE
FMUTE
**
**
**
**
**
**
**
**
D4
INTS
D3
CSWP
NOTES
JS0 no mute action
JS1 mutes mono and enables
all rear.
STANDARD 6 CHAN CONFIG
swapped HP_OUT and
LINE_OUT
**RESERVED
**RESERVED
Default
Default
Default
Default
Default
Default
D2
SPAL
D1
SPDZ
D0
SP
LNK
AD1986
Default
0x1001