AD1986 Analog Devices, AD1986 Datasheet - Page 27

• Manufacturer Part Number: AD1986
• Manufacturer: Analog Devices

Preliminary Technical Data
Register
REF (RO)
(Voltage
References, V
and VREF_OUT
status (read
only))
PR0
PR1
PR2
PR3
PR4
PR5
PR6
EAPD
x
EXT’D AUDIO ID (REGISTER 0x28)
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one
or more of the extended audio features are supported.
Reg
0x28
Table 47.
Register
VRA (RO)
SPDIF (RO)
DRA (RO)
DSA [1:0]
Name
Ext’d Audio ID
REF
ADC
VREF_OUT pin output states controlled by the CV
REF
0
1
All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.
Default: all ADCs and input muxs powered on (0x0).
All DACs power down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of PR3.
Default: all DACs and EQ powered on (0x0).
Analog mixer power down. (valid if PR7 = 0).
Default: analog mixer powered on (0x0).
All V
not powered down, setting this bit will have no effect on the V
Default: All VREFand VREF_OUT pins powered on (0x0).
AC-Link Interface power down. The reference and the mixer can be either up or down, but all power-up sequences
must be allowed to run to completion before PR5 and PR4 are both set. In multiple-CODEC systems, the master
CODEC’s PR4 bit controls the slave CODEC. In the slave CODEC the PR4 bit has no effect except to enable or disable PR5.
Default: AC-link Interface powered on (0x0).
Internal Clocks disabled.
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (e.g. PR0, PR1, PR4). The reference and the
mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4
are both set. In multiple CODEC systems, the master CODEC’s PR5 controls the slave CODEC. PR5 is effective in the slave
CODEC if the master's PR5 bit is clear.
Default: internal clocks enabled (0x0).
Powers down the headphone amplifiers.
Default: HP amp powered on (0x0).
EAPD
0
1
Reserved.
D15
ID1
Description
Variable rate PCM audio: read only
SPDIF support: read only
Double rate audio: read only
DAC slot assignment (read/write)
DSA [1:0]
00
01
10
11
REF
and V
D14
ID0
REF
D13
x
_OUT pins power down. May be used in combination with PR2 or by itself. If all the ADCs and DACs are
ADC Status
V
Voltage References, VREF and VREF_OUT not ready.
Voltage References, VREF, and VREF_OUT up to nominal level.
EAPD Pin Status
Sets the EAPD pin low, enabling an external power amplifier.
Sets the EAPD pin high, shutting the external power amplifier off.
D12
X
REF
Left
3
7
6
10
Status
D11
REV1
Front DAC
D10
REV0
Right
4
8
9
11
Rev. 0 | Page 27 of 52
D9
AMAP
REF
D8
LDAC
Setting
Left
7
6
10
3
, MV
= 1
= 1
= 1
Surround DAC
REF
D7
SDAC
, and LV
Function
Variable rate PCM audio supported
SPDIF transmitter supported (IEC958)
Double rate audio supported for DAC0 L/R
Right
8
9
11
4
REF
D6
CDAC
and will only power down VREF_OUT.
REF
controls in Register 0x70.
D5
DSA1
Left
6
10
3
7
D4
DSA0
C/LFE DAC
D3
x
Right
9
11
4
8
Default
Default: 0
SPDF
D2
D1
DRA
Default
Default
D0
VRA
AD1986
Default
0x0BC7