W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 22

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
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Features :
Related Pins :
- SDI
- SDO (output) : This pin contains the output data shifted to external audio/telephony codec devices
- SYNC (in/out) : This pin is the frame synchronization signal between SSI and codec devices. The SYNC may be
- SCLK (in/out) : This pin is the serial bit clock between SSI and codec devices. Likewise, The SCLK may be
Operation Modes :
- Master Mode : Once CFGH[2] is set to logic 1 and MD[25] is pull high, SSI is operated in master mode, and the
- Slave Mode : Once CFGH[2] is set to logic 0 and MD[25] is pull down, SSI is operated in slave mode, the SCLK
- Loop mode : This mode (CFGH[1] =1) aims at selftesting. When this bit is set, serial data-out "SDO" is connected
- Long Framing : When CFGH[3] is set to logic 1, SSI is operated in long framing mode. The following features
are
supports "long framing" and "short framing" (synchronous, frame-based protocol)
provides "master mode" and "slave mode"
build-in two 48x16 (or 24x32) data fifo to accelerate transmit/receive operation
programable data bits per one frame (sampling rate) : 1 ~ 256 bits/frame
programable data bits per word (resolution of each sampling) : 1 ~ 32 bits/word
programable multi-word (per frame) transfer : 1 ~ 16 words/frame
(input) : This pin contains the input data shifted from external audio/telephony codec devices
input or output depending on SSI operated in slave- or master-mode respectively.
to serial data-in "SDI" internally and SDO pin fixed at logic 0 state. Besides, if Loop and Master
mode are chose concurrently, SSI module will not issue SYNC until TX-FIFO contains at least one
data word.
SYNC (determines the sampling rate) and SCLK is drived by SSI module to external codec devices.
and SYNC are drived externally (may be from codec devices). So the sampling rate and SCLK fre-
quence are determined by external devices, however software driver still need to properly set "serial
data bit length" (CFGH[8:10] ) as well as "data words per frame" ( CFGH[12:15] ) to make SSI
module working correctly.
consists of the following features.
- The SSI module always samples receive date (SDI) on the falling edge of SCLK, whereas always
- The frame sync (SYNC) is asserted immediately as the first bit of transmit and receive data.
- The frame sync (SYNC) is asserted for one "serial word length" which determined by
- The frame sync rate (sampling rate) and SCLK frequence follow eq (5.1.6b) and (5.1.6a)
- The transmit FIFO and receive FIFO is configued as 48x16 if "serial word length" <= 16,
included in long framing mode :
input or output depending on SSI operated in slave- or master-mode respectively.
CFGH[8:11].
respectively on master mode and determined by external devices on slave mode.
and will be configured as 24x32 if "serial word length" > 16.
pushes transmit data (SDO) on the rising edge of SCLK.
SCLK frequence = EXTCLK/[2*(CFGL[8:15] + 1)]
SYNC period
Serial word length = CFGH[8:11] + 1
= SCLK * (CFGL[0:7] + 1)
(5.1.6a)
(5.1.6b)
(5.1.6c)
W90220F
Version 0.84