W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 9

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
9
PPAR
DMA Interface
DREQ0
DREQ1
DACK0
DACK1
DMARDY
CS0
CS1
IOR
IOW
TC0
TC1
DD[0:7]
ECP Interface
Busy
nFault
nAck
PError
Select
nSelectIn
nInit
nAutoFd
nStrobe
ED[0:7]
Memory Controller Interface
RAS#[0:1]
I/O
I
O
I
O
O
O
O
I/O
I
I
I
I
I
O
O
O
O
I/O
O
79
127
128
134
135
106
129
130
108
107
109
111
126-119
151
153
154
155
156
145
147
148
150
144-137
11, 13
PCI Parity is even parity across PDA[31:0] and C/BE[3:0]#.
PPAR is stable and valid one clock after the address phase.
For data phases, PPAR is stable and valid one clock after
either IRDY# is asserted on a write transaction or TRDY# is
asserted on a read transaction. (PPAR has the same timing
as PDA[31:0], but it is delayed by one clock.) The mater
drives PPAR for address and write data phases; the target
drives PPAR for read data phase.
DMA Request signals request an external transfer on DMA
channel 0 (DREQ0) or DMA channel 1 (DREQ1).
DMA Acknowledge signals acknowledge an external transfer
on DMA channel 0 (DREQ0) or DMA channel 1 (DREQ1).
DMA Device Ready signal is used to extend the length of
DMA bus cycles. If a device wants to extend the DMA bus
cycles, it will force the DMARDY signal low when it decodes
its address and receives a IOR or IOW command.
DMA Chip Select signals select the corresponding I/O
devices for programming or DMA transfers.
DMA I/O read signal is used to indicate to the I/O device that
the present bus cycle is an I/O read cycle.
DMA I/O write signal is used to indicate to the I/O device that
the present bus cycle is an I/O write cycle.
Terminal count for DMA channels, the pin is driven active for
one clock when byte count reaches zero and after the last
transfer for a DAM has completed.
8-bit DMA I/O Data bus, bit 0 is the most significant bit.
For more detail description of the ECP interface signals,
please refer to the IEEE P1284 Standard
ECP busy input signal
ECP fault input
ECP acknowledge input
ECP parity error
ECP Select
ECP select output
ECP initialization
ECP Autofeed
ECP Strobe
Bi-directional ECP Data bus, ED[0] is the most significant bit
(msb).
DRAM Row Address Strobe, Banks 0-1. These signals are
used to select the DRAM row address. A High-to-Low
transition on one of these signals causes a DRAM in the
corresponding bank to latch the row address and begin an
access.
W90220F
Version 0.84