W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 64

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
64
Line Status Register (LSR)
Port address : 0xf00003fd (COM1)
Err_RCVR
Bits 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
0
RX FIFO Error
Transmitter Empty
Transmitter Holding Register Empty
Break Interrupt indicator
Framing Error indicator
Parity Error indicator
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE) or break indication (BI)
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter Shift Register
1 = Both THR and TSR are empty.
0 = THR is not empty.
1 = THR is empty.
The THRE bit is set when the last data word of TX FIFO is transferred to TSR. This bit is reset
concurrently with the loading of the THR (or TX FIFO) by the CPU. This bit also causes the
UART to issue an interrupt (Irpt_THRE) to the CPU when IER[6]=1.
This bit is set to a logic 1 whenever the received data input is held in the "spacing state"
(logic 0) for longer than a full word transmission time (that is, the total time of "start bit"
+ data bits + parity + stop bits).
This bit is set to a logic 1 whenever the received character did not have a valid "stop bit"
(that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
0xf00002fd (COM2)
TEMT
in the FIFO. LSR[0] is cleared when CPU reads the LSR and if there are no sub-
sequent errors in the RX FIFO.
(TSR) are not empty.
1
THRE
2
BI
3
Read only
FE
4
Power-on Default : ---
PE
5
OE
6
DR
7
W90220F
Version 0.84