W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 149

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

FIFO Control Register (FCR)
Port address: 0xf000037c
Bit 0
Bit 1
Bit 2
Bit 3
Bits 4-5
Bits 6-7
W90221X version 0.6
DMAen
0
0
1
FRST
1
DMA mode enable
A low-to-high transition on this bit will make PPI issue a DREQ to
DMA controller. Upon receiving the corresponding DACK, PPI
deasserts the DREQ. This bit will be cleared by DMA terminal-count
(TC) asserting or by a CPU write cycle with data-in[0] = 0.
Reset DFIFO
Writing a logical one to this bit will assert "DFIFO Reset" for one
EXTCLK cycle. This bit will return to deasserted state automatically
after "DFIFO Reset" is issued.
Reset device
Writing a logical one to this bit will assert "Device Reset" for one
EXTCLK cycle. This bit will return to deasserted state automatically
after "Device Reset" is issued.
PWord (PWord defines the basic unit of DFIFO access during CPU
cycle)
PWord is 8-bit (one byte)
PWord is 32-bit (four bytes)
Device mode select
IER[1] and FCR[4:5] are used to choose device operation mode
DFIFO read threshold
These two bits define the threshold level for triggering data-available
interrupt (Irpt_RDA) of DFIFO during reverse transferring.
{IER[1], FCR[4:5]}
DRST
2
1X0
1X1
000
001
010
011
Access type: read/write
PWord
3
Test Mode
Peripheral Emulation Mode
Standard Mode
PS2 Mode
Fast Standard Mode
ECP Mode
4
Device Operation Mode
MOD
5
6
RDTH
Default: 0x0
7
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