W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 29

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

5.8 DMA CONTROLLER
5.8.1 Features
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5.9 PCI BRIDGE
5.9.1 Overview
The W90221X host bridge provides a PCI bus interface that is compliant with the PCI local
bus specification, revision 2.1. The implementation is optimized for high performance data
streaming when the W90221X is acting as either the target or the initiator on the PCI bus.
5.9.2 Features
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5.9.3 Relates Pins
PCLK (In)
FRAME# (In/Out)
PDA[31:0] (In/Out)
W90221X version 0.6
The video pos-processing(VPOST) block that is designed to support two kind of display
devices, TV and Monitor. On TV Mode, when TVTWH[12:13] is set to 1X, W90221X
operate on TV-system. Clock (DPCLK) is equal to 27MHz. On Monitor Mode, when
TVTWH[12:13] is set to 0X, W90221X operate on Monitor mode. Clock (GFXCLK) is
equal to 36.864MHz.
Flexible block-transfer mode and demand mode are supported
Provides 8-bit ECP-to-memory or memory-to-ECP transfer mode
Provides 8-, 16- and 32-bit memory-to-memory transfer modes
DMA transfer between PCI memory to/from system memory are also support
4 words (16 bytes) memory burst-access; linear burst order
Build-in 4-words data FIFO to accelerate memory access
The starting address of source and target shall be half-word boundary for 16-bit memory
transfer and word
Boundary for 32-bit memory transfer
Supports up to four external PCI bus masters
Programmable external PCI clock signal (PCICLK) delay relative to internal PCI clock
signal (EXTCLK)
Provides fix/rotate arbitration algorithms
Provides configuration read/write, I/O read/write, and memory read/write accesses
PCLK provides timing for all transactions on PCI and is an input to every PCI device.
Cycle Frame, FRAME#, is an output when W90221X acts as an initiator on the PCI bus.
FRAME# is driven by the current initiator and indicates the start (when it’s first asserted) and
duration (the duration of its assertion) of a transaction. While FRAME# is asserted, data transfer
continue. When FRAME# is de-asserted, the transaction is in the final data phase or has
completed. FRAME# is an input when W90221X acts as a PCI target.
These signals are connected to the PCI address/data bus. Address is driven by W90221X with
FRAME# being asserted; data is then driven or received in the following clocks. When
W90221X acts as a target on the PCI bus, the AD[31:0] signals are inputs and contain the
address during the first clock cycle of FRAME# assertion and input data(writes) or
output data(reads) on subsequent clocks.
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