W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 30

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

C/BE#[3:0] (In/Out)
IRDY# (In/Out)
TRDY# (In/Out)
STOP# (In/Out)
DEVSEL# (In/Out)
PERR# (In/Out)
PPAR# (In/Out)
REQ0# (In)
W90221X version 0.6
PCI bus command and byte enable signals are multiplexed on the same lines. The
Command/Byte Enable bus, C/BE#[3:0], defines the type of transaction during the
address phase of a transaction. During the data phase, C/BE#[3:0] is used as byte
enable signals. The byte enable signals determine which data paths carrying meaningful
data. The PCI command types that are acknowledged by the W90221X are listed below:
Initiator Ready, IRDY#, is an output when W90221X acts as an initiator on the PCI bus
and an input when W90221X acts as a PCI target. During a write, IRDY# asserted
indicates that the initiator is driving valid data onto the data bus. During a read, IRDY#
asserted indicates that the initiator is ready to accept data from the current-addressed
target.
Target Ready, TRDY#, is an input when W90221X acts as an initiator on the PCI bus
and an output when W90221X acts as a PCI target. It is asserted when the target is
ready to complete the current data phase (data transfer). A data phase is completed
when the target is asserting TRDY# and the initiator is asserting IRDY# at the rising-
edge of the PCICLK signal.
STOP# is an input when W90221X acts as an initiator on the PCI bus and an output
when W90221X acts as a PCI target. STOP# is used for disconnect, retry, and abort
sequences on the PCI bus.
Device select, when asserted, indicates that a PCI target device has decoded its
address as the target of the current access. The W90221X asserts DEVSEL# based on
the DRAM address range being accessed by a PCI initiator. As an input it indicates
whether any device on the bus has been selected.
PERR# indicates the current transaction has data parity error occurs. It is an input when
W90221X acts as an PCI initiator and the current transaction is write access or
W90221X acts as an PCI target and the current transaction is read access. it is an
output when W90221X acts as PCI initiator and the current transaction is read access or
W90221X acts as an PCI target and the current transaction is write access. When
PERR# asserted and Master 0 Latency Register bit 17=1, it will generate MI (non-
maskable interrupt).
PPAR# is driven by the W90221X when it acts as a PCI initiator during address and
data phases for a write cycle, and during the address phase for a read cycle. PPAR is
driven by the W90221X when it acts as a PCI target during each data phase of a PCI
memory read cycle. Even parity is generated across PDA[31:0] and COMBE#[3:0].
C/BE3#
0
0
0
0
1
1
C/BE2#
0
0
1
1
0
0
C/BE1#
1
1
1
1
1
1
C/BE0#
0
1
0
1
0
1
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Command Type
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