XC9500XV Xilinx Corp., XC9500XV Datasheet - Page 3

• Manufacturer Part Number: XC9500XV
• Description: XC9500XV 2.5 V CPLD Family
• Manufacturer: Xilinx Corp.

Table 2: XC9500XV Packages and User I/O Pins (not including four dedicated JTAG pins)
Function Block
Each Function Block, as shown in
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the Fast CONNECT II
switch matrix. These 18 outputs and their corresponding
output enable signals also drive the IOB.
DS049 (v2.1) June 24, 2002
Preliminary Product Specification
44-pin PLCC
44-pin VQFP
48-pin CSP
100-pin TQFP
144-pin CSP
144-pin TQFP
208-pin PQFP
256-pin FBGA
280-pin CSP
Fast CONNECT II
Switch Matrix
R
From
54
Figure 2
Programmable
AND-Array
XC9536XV
Figure 2: XC9500XV Function Block
is comprised of
34
34
36
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-
-
-
-
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www.xilinx.com
Allocators
1-800-255-7778
Product
Term
Set/Reset
XC9572XV
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Global
Macrocell 18
1
Macrocell 1
34
34
38
72
-
-
-
-
-
Clocks
Global
3
XC9500XV Family High-Performance CPLD
XC95144XV
18
18
18
117
117
81
-
-
-
-
-
-
OUT
PTOE
To Fast CONNECT II
Switch Matrix
To I/O Blocks
XC95288XV
DS049_02_041400
117
168
192
192
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-
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3