BGA7351,115 NXP Semiconductors, BGA7351,115 Datasheet - Page 5

• Manufacturer Part Number: BGA7351,115
• Description: Specifications: Type: Variable Gain Amplifier ; Applications: Wireless ; Package / Case: 32-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: NXP Semiconductors

8
Features
Release for production
CMOS/Bipolar
LV NPN f
HV NPN f
NPN BVce0: HV/LV **
V-PNP f
CMOS Voltage /
Dual Gate
Noise figure NPN (dB)
RFCMOS f
Isolation (60 dB @ 10 GHz)
Interconnection
(AlCu with CMP W Plugs)
Capacitors
Resistors (Ω/sq)
Varicaps (single-ended &
differential)
Inductors (1.5 nH @
2 GHz) - scalable
Other devices
Mask count
BiCMOS
f /f
QUBiC4Xi
QUBiC4X
QUBiC4+
T
max
T
/ BVcb0 (GHz / V)
/F
T
/F
T
max
(GHz)
max
= 37/90 GHz
(GHz)
(GHz)
Q > 21, Thick Metal, Deep trench isolation,
Poly (64/220/330/2K), Active (12, 57),
SiGe:C
f
SiGe:C
f / f
T
T
CMOS 0.25 µm, Bipolar 0.4 µm,
Double poly, Deep trench, Si
f
max
max
High Precision SiCr (270)
2x single ended, Q > 40
3x differential, Q 30-50
LPNP, Isolated NMOS
31 / 32 (MIM) / 33 (DG)
5 LM, 3 µm top Metal
NMOS 58, PMOS 19
NW, DN, Poly-Poly
= 180/200 GHz
= 137/180 GHz
High R substrate
5 fF/µm
STI and DTI
QUBiC4+
5.9 / 3.8 V
2.5 / 3.3 V
2 GHz: 1.1
37/90 (Si)
28/70 (Si)
7 / >9
2004
2
MIM
+HVNPN
+VPNP
-4ML
+TFR
+DG
Q > 21, Thick Metal, Deep trench isolation,
Poly (64/220/330/2K), Active (12, 57),
CMOS 0.25 µm, Bipolar LV 0.4 µm,
Double poly, Deep trench, SiGe:C
QUBiC4+
` Baseline, 0.25 µm CMOS, single poly, 5 metal
` Digital gate density 26k gates/mm
` f
` +TFR – Thin Film Resistor
` +DG – Dual Gate Oxide MOS
` +HVNPN – High Voltage NPN
` +VPNP – Vertical PNP (high V
` -4ML – high density 5 fF/µm
` Wide range of active and high quality passive devices
` Optimized for up to 5 GHz applications
QUBiC4X
` SiGe:C process
` f
` Optimized for up to 30 GHz applications
` Transformers
QUBiC4Xi
` SiGe:C process
` Improves f
` Optimized for ultra-low noise for microwave above 30 GHz
High Precision SiCr (270)
2x single ended, Q > 40
3x differential, Q 30-50
5 LM, 3 µm top Metal
NMOS 58, PMOS 19
T
T
NW, DN, Poly-Poly
/f
/f
137/180 (SiGe:C)
High R substrate
60/120 (SiGe:C)
Isolated-NMOS
MAX
MAX
5 fF/µm
STI and DTI
10 GHz: 0.8
QUBiC4X
3.2 / 2.0 V
2 µm M4
35 (MIM)
planned
= 37/90 GHz
= 137/180 GHz
2006
2.5 V
2
MIM
T
/f
max
up to 180/200 GHz
Q > 21, Thick Metal, Deep trench isolation,
2
early
MIM capacitor
Poly (64/220/330/2K), Active (12, 57),
CMOS 0.25 µm, Bipolar LV 0.3 µm,
Double poly, Deep trench, SiGe:C
)
High Precision SiCr (270)
2x single ended, Q > 40
2
3x differential, Q 30-50
LPNP, Isolated-NMOS
5 LM, 3 µm top Metal
NMOS 58, PMOS 19
NW, DN, Poly-Poly
180/200 (SiGe:C)
High R substrate
5 fF/µm
tbd (SiGe:C)
10 GHz: 0.5
STI and DTI
QUBiC4X
2.5 / 1.4 V
planned
35 (MIM)
2008
2.5 V
2
MIM
High-speed data converters
Our highly competitive high-speed ADCs and DACs feature three different data interfaces, including the industry’s first
implementation of JEDEC JESD204A (2008). This new standardized serial interface dramatically reduces the number of interconnect
signals between data converters and logic devices. It also solves one of the major base station (and other I/Q modulation
communications systems) design challenges by synchronously bonding multiple data channels or lanes.
The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low
power at sample rates up to 125 Msps. A pipelined architecture and output error correction ensure the ADC1413D is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.8 V
source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A standard. An
integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADCs. A set of IC configurations is also available
via the binary level control pins, which are used at power-up. The device also includes a programmable full-scale SPI to allow
a flexible input voltage range of 1 to 2 V (peak-to-peak). Excellent dynamic performance (SNR=71.4 Db, SFDR=87 dBc typ) is
maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1413D ideal for use in communications,
imaging, and medical applications.
The DAC1408D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable, 2x, 4x or 8x
interpolating filters optimized for multi-carrier WCDMA transmitters up to 750 Msps. Thanks to its digital on-chip modulation,
the DAC1408D750 allows the complex pattern provided through the lanes to be converted up from baseband to IF. The mixing
frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is
controlled by a 16-bit register. The serial input digital interface (maximum data rate of 3.125 Gbps) is compliant with the JEDEC
JESD204A standard. NXP’s implementation of Multiple Device Synchronization (MDS) enables the data streams of several DACs
to be sample synchronized and phase coherent.
CVG – The industry’s first implementation of the JESD204A serial interface
CGV™ (Convertisseur Grande Vitesse), NXP’s 100% JEDEC JESD204A-compliant interface that NXP enhanced for even greater
ease-of-use and improved performance:
ADC1413D125 Demoboard
` Enhanced rate (up to 4.0 Gbps) − a 28% increase over the JEDEC standard 3.125 Gbps
` Enhanced reach (up to 100 cm) − a 400% increase over the JEDEC standard 20 cm
` Enhanced features (multiple DAC synchronization) − enables up to sixteen DAC data streams to be
` Comprehensive interoperability with SERDES-based FPGAs − eliminates the risk and cost associated
` NXP CGV ADCs and DACs support FPGAs from Altera, Lattice and Xilinx −giving you plug-and-play interop!
sample-synchronized and phase-coherent
with project schedules
ADCs
Our single- and dual-channel ADC portfolio offers more than 80 different
ADCs with resolutions from 8 to 16 bits, input samples rates from 20 to
125 Msps, optional input buffer and low-voltage CMOS, LVDS/DDR and
JEDEC JESD204A digital outputs.
DACs
Our dual-channel DACs portfolio offers DACs with resolutions of 10, 12
or 14 bits, output samples rates from 125 to 750 Msps, and low-voltage
CMOS, LVDS/DDR or JEDEC JESD204A digital inputs.
9