LPC1758 NXP Semiconductors, LPC1758 Datasheet
LPC1758
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LPC1758 Summary of contents
Page 1
... SRAM on the CPU with local code/data bus for high-performance CPU access. Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Objective data sheet ...
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... N N LPC1758_56_54_52_51_2 Objective data sheet On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller. USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only. ...
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... Code Read Protection (CRP) with different security levels. I www.DataSheet4U.com Available as 80-pin LQFP package (12 3. Applications I eMetering I Lighting I Industrial networking I Alarm systems I White goods I Motor control LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 12 1.4 mm). Rev. 02 — 11 February 2009 © NXP B.V. 2009. All rights reserved ...
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... USB SRAM 64 kB yes Device/ Host/OTG Device/ Host/OTG Device/ Host/OTG Device only Device only Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller CAN I S-bus DAC Package 2 yes yes 80 pins 2 yes yes ...
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... SSP0 UART2/3 (1) I2S I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM (3) DAC QUADRATURE ENCODER (1) LPC1758/56 only (2) LPC1758 only (3) LPC1758/56/54 only (4) LPC1752/51 USB device only 002aae153 © NXP B.V. 2009. All rights reserved. CLKOUT SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 1 I2SRX ...
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... SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 60 41 002aae158 2 C-bus compliant open-drain pin). 2 C-bus compliant open-drain pin). 2 S-bus specification . (LPC1758/56 © NXP B.V. 2009. All rights reserved ...
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... MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 2 S-bus specification . (LPC1758/56 2 S-bus specification . (LPC1758/56 2 S-bus specification . (LPC1758/56 © NXP B.V. 2009. All rights reserved ...
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... P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1758 only). I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1758 only). I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1758 only). I/O P1[9] — General purpose digital input/output pin. ...
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... SCK0 — Serial clock for SSP0. I/O P1[22] — General purpose digital input/output pin. O MC0B — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch). (LPC1758/56/54 only). O MAT1[0] — Match output for Timer 1, channel 0. I/O P1[23] — General purpose digital input/output pin. ...
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... RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1758/56 only). O RTS1 — Request to Send output for UART1. Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2009. All rights reserved. ...
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... TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC1758/56/54/52/51 being in Reset state. I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... The LPC1758/56/54/52/51 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters ...
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... AHB-Lite buses. 7.4 On-chip SRAM The LPC1758/56/54/52/51 contain a total on-chip static RAM memory. This includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix ...
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... The APB peripheral area size and is divided to allow for peripherals. Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral. www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Rev. 02 — 11 February 2009 © NXP B.V. 2009. All rights reserved ...
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... AHB SRAM0 (LPC1758/6/4) 0x2007 C000 reserved 0x1FFF 2000 8 kB boot ROM 0x1FFF 0000 reserved 0x1000 8000 32 kB local static RAM (LPC1758) 0x1000 4000 16 kB local static RAM (LPC1756/4/2) 0x1000 2000 8 kB local static RAM (LPC1751) 0x1000 0000 reserved 0x0008 0000 ...
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... AHB master. The GPDMA controller allows data transfers between the USB and Ethernet (LPC1758 only) controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I and the DAC ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC1758/56/54/52/51 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral and are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • ...
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... Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.11 Ethernet (LPC1758 only) The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, fl ...
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... All transactions are initiated by the host controller. The LPC1758/56/54 USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in www ...
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... NXP Semiconductors • While USB is in the Suspend mode, the LPC1758/56/54/52/51 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.14 12-bit ADC The LPC1758/56/54/52/51 contain one ADC single 12-bit successive approximation ADC with four channels and DMA support. 7.14.1 Features • 12-bit successive approximation ADC. ...
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... All UARTs have DMA support. 7.17 SPI serial I/O controller The LPC1758/56/54/52/51 contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single www.DataSheet4U.com master and a single slave can communicate on the interface during a given data transfer. ...
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... DMA transfers supported by GPDMA 2 7.19 I C-bus serial I/O controllers The LPC1758/56/54/52/51 each contain three I The I (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC1758/56/54/52/51 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specifi ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1758/56/54/52/51. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
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... Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Rev. 02 — 11 February 2009 © NXP B.V. 2009. All rights reserved ...
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... System tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception interval. In the LPC1758/56/54/52/51, this timer can be clocked from the internal AHB clock or from a device pin. 7.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘ ...
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... RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1758/56/54/52/51 is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1758/56/54/52/51 use the IRC as the clock source. Software may later switch to one of the other available clock sources. ...
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... PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 7.29.3 USB PLL (PLL1) The LPC1758/56/54/52/51 contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only ...
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... Power control The LPC1758/56/54/52/51 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfi ...
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... The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC1758/56/54/52/51 can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. www.DataSheet4U.com 7 ...
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... NXP Semiconductors 7.29.8 Power domains The LPC1758/56/54/52/51 provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC1758/56/54/52/51, I/O pads are powered by the 3 the V the CPU and most of the peripherals. ...
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... Fig 5. 7.30 System control 7.30.1 Reset Reset has four sources on the LPC1758/56/54/52/51: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating ...
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... Code security (Code Read Protection - CRP) This feature of the LPC1758/56/54/52/51 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated fl ...
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... CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet (LPC1758 only) and USB, can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions ...
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... The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [1] Conditions [4] per supply pin [4] per ground pin (0.5V ) < ...
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... C), amb = the package junction-to-ambient thermal resistance ( C/W) th(j-a) = sum of internal and I/O power dissipation D Conditions LQFP80 package Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller ( C), can be calculated using the following J and V . The I/O power dissipation Min Typ Max - < ...
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... I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Conditions Min core and external rail 2.4 2.4 2.7 [2] 2.1 2 on-chip pull- resistor disabled = V ; on-chip - I DD(3V3) pull-down resistor ...
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... V = 3.3 V; DD(REG)(3V3 amb deep power-down mode 3.3 V; DD(REG)(3V3 amb RTC running; V present DD(REG)(3V3) RTC running; V not present DD(REG)(3V3) Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [1] Min Typ Max - <tbd> <tbd> <tbd> <tbd> <tbd> < ...
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... V < V < includes V range 1 3 GND L with 33 series resistor; steady state drive SoftConnect = ON drops below 1.6 V. i(VBAT) is grounded. DD(3V3 and D . Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [1] Min Typ Max - - 5.25 0 0.8 - 2.5 0 0.18 2 ...
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... Conditions active mode entered executing code from flash; all peripherals enabled amb but not configured to run. Regulator supply current at different core voltages in active mode Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) 001aac984 (X) © ...
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... Typical peripheral current consumption = 25 C; all measurements in A; PCLK = amb CCLK = 10 MHz active mode sleep mode active mode sleep mode <tbd> <tbd> <tbd> <tbd> Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) 001aac984 ( RTC running; ...
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... RIT UART0 UART1 UART2 UART3 PWM1 Motor control PWM Quadrature encoder 2 I C1-bus 2 I C2-bus 2 I S-bus interface (LPC1758/56 only) SPI SSP0 SSP1 CAN1 CAN2 (LPC1758/56 only) ADC DAC (LPC1758/56/54 only) USB Ethernet (LPC1758 only) GPDMA controller www.DataSheet4U.com Table 8. V i(VBAT) I ...
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... LOW-level output ( <tbd> Measured on pins Pn. x.x V. DD(3V3) current versus HIGH-level output voltage V OH Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) OL 001aac984 (X) © NXP B.V. 2009. All rights reserved ...
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... DD(3V3) versus input voltage ( <tbd> Measured on pins Pn. x.x V. DD(3V3) versus input voltage V pd Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 001aac984 (X) i 001aac984 (X) i © NXP B.V. 2009. All rights reserved ...
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... Objective data sheet Conditions + +85 C powered; < 100 cycles +85 C [1] over specified ranges. Conditions t t CHCL CLCX T cy(clk) i(RMS) Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Min Typ Max 10000 - - 100000 - - [2] Min Typ ...
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... conditions: <tbd> ( <tbd> conditions: <tbd> Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> 001aac984 (X) 001aac984 (X) © NXP B.V. 2009. All rights reserved. ...
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... Conditions LOW HD;STA HIGH SU;DAT Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max [ 0 <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...
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... Objective data sheet [1] over specified ranges. Conditions amb measured in SPI Master mode; see Figure 18 t su(SPI_MISO) Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller [2] Min Typ Max - 11 - sampling edges 002aad326 © NXP B.V. 2009. All rights reserved. Unit ...
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... Figure must reject as EOP; see Figure 19 must accept as EOP; see Figure 19 crossover point extended crossover point differential data to SE0/EOP skew PERIOD FDEOP Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 ...
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... Fig 20. SPI master timing (CPHA = 1) LPC1758_56_54_52_51_2 Objective data sheet T t SPICYC SPICLKH t SPIQV DATA VALID MOSI t SPIDSU MISO DATA VALID Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Min Typ Max <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...
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... DATA VALID MOSI t SPIDSU DATA VALID MISO T t SPICYC SPICLKH t SPIDSU MOSI DATA VALID t SPIQV MISO DATA VALID Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller t t SPICLKH SPICLKL t SPIOH DATA VALID t SPIDH DATA VALID 002aad987 t SPICLKL t SPIDH DATA VALID t ...
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... Fig 23. SPI slave timing (CPHA = 0) www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet T SPICYC t SPIDSU MOSI DATA VALID DATA VALID t SPIQV MISO DATA VALID DATA VALID Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller t t SPICLKH SPICLKL t SPIDH t SPIOH 002aad989 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 11.8 Ethernet (LPC1758 only) Table 16. Dynamic characteristics: Ethernet MAC pins Symbol Parameter Ethernet MAC signals for MIIM T clock cycle time cy(clk) t data output valid time v(Q) t data output high-impedance time QZ t data input set-up time su(D) t data input hold time h(D) Ethernet MAC signals for RMII ...
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... Fig 24. Ethernet MAC MIIM timing ENET_REF_CLK ENET_TX_EN ENET_TXD[1:0] ENET_RXD[1:0] ENET_RX_ER Fig 25. Ethernet RMII timing www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet T cy(clk) ENET_MDC t v(Q) ENET_MDIO(O) ENET_MDIO(I) t d(QV su(D) h(D) ENET_CRS Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller su(D) h(D) 002aad990 t h(Q) 002aad991 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 2 11.9 I S-bus interface (LPC1758/56 only) Table 17. Dynamic characteristics +85 C. amb Symbol Parameter common to input and output T clock cycle time cy(clk) t rise time r t fall time f output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
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... NXP Semiconductors I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 27. I www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet T cy(clk su(D) 2 S-bus timing (input) Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller h( su(D) su(D) © NXP B.V. 2009. All rights reserved 002aae159 ...
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... See the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 28. Figure 28. Figure 28. Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller Min Typ Max DDA - - < ...
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... LSB (ideal (LSB ) IA ideal ). D ). L(adj) Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller offset error E (1) 4090 4091 4092 4093 4094 4095 V V DDA SSA 1 LSB = 4096 © NXP B.V. 2009. All rights reserved. gain error ...
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... NXP Semiconductors AD0[y] Fig 29. Suggested ADC interface - LPC1758/56/54/52/51 AD0[y] pin www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet LPC17XX x k SAMPLE Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller R vsi AD0[y] V EXT 002aad949 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 13. DAC electrical characteristics (LPC1758/56/54 only) Table 19. DAC electrical characteristics +85 C unless otherwise specified; DAC frequency <tbd> MHz. DDA amb Symbol Parameter PSRR power supply rejection ratio V output voltage O E differential linearity error D E integral non-linearity ...
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... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Fig 30. LPC1758/56/54/52/51 USB interface on a self-powered device www.DataSheet4U.com Fig 31. LPC1758/56/54/52/51 USB interface on a bus-powered device LPC1758_56_54_52_51_2 Objective data sheet V DD(3V3) USB_UP_LED USB_CONNECT LPC17xx SoftConnect switch R1 1 BUS USB_D USB_D DD(3V3) ...
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... NXP Semiconductors RSTOUT LPC1758/56/54 SCL1/2 SDA1/2 EINT0 USB_D+ USB_D Fig 32. LPC1758/56/54 USB OTG port configuration LPC1758/56/54 www.DataSheet4U.com Fig 33. LPC1758/56/54 USB host port configuration LPC1758_56_54_52_51_2 Objective data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED SUSPEND SCL SDA ...
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... NXP Semiconductors LPC17xx Fig 34. LPC1758/56/54/52/51 USB device port configuration www.DataSheet4U.com LPC1758_56_54_52_51_2 Objective data sheet V DD USB_UP_LED V DD USB_CONNECT 33 USB_D+ 33 USB_D V BUS Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller USB-B D connector V BUS 002aad943 © NXP B.V. 2009. All rights reserved. ...
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... scale (1) ( 0.27 0.18 12.1 12.1 14.15 14.15 0.5 0.13 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller detail ( 0.75 1.45 1 0.2 0.15 0.1 0.30 1.05 EUROPEAN PROJECTION SOT315 ( ...
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... Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2009. All rights reserved ...
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... LPC1758_56_54_52_51_2 Objective data sheet Release date Data sheet status 20090211 Objective data sheet • Updated Figure 3 “LPC1758/56/54/52/51 memory map” on page 15 • Updated Table 9 “Flash characteristics” on page 47 20090115 Objective data sheet Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 11 February 2009 LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2009. All rights reserved ...
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... SSP serial I/O controller . . . . . . . . . . . . . . . . . 22 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 7.19 I C-bus serial I/O controllers 7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LPC1758_56_54_52_51_2 Objective data sheet LPC1758/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 2 7.20 I S-bus serial I/O controllers (LPC1758/56 only 7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 25 7.22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 26 7.24 Quadrature Encoder Interface (QEI 7.24.1 Features ...
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... USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.8 Ethernet (LPC1758 only 11.9 I S-bus interface (LPC1758/56 only ADC electrical characteristics . . . . . . . . . . . . 59 13 DAC electrical characteristics (LPC1758/56/54 only Application information 14.1 Suggested USB interface solutions . . . . . . . . 63 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 66 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 67 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 68 18 Legal information 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 69 18.2 Defi ...