LPC2129 NXP Semiconductors, LPC2129 Datasheet
LPC2129
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LPC2129 Summary of contents
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LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN Rev. 06 — 10 December 2007 1. General description The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with ...
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... NXP Semiconductors I 64/128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms. ...
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... LPC2129FBD64/00 LPC2129FBD64/01 3.1 Ordering options Table 2. Type number LPC2109FBD64/ LPC2109FBD64/ LPC2119FBD64 LPC2119FBD64/00 128 kB LPC2119FBD64/01 128 kB LPC2129FBD64 LPC2129FBD64/00 256 kB LPC2129FBD64/01 256 kB LPC2109_2119_2129_6 Product data sheet Ordering information …continued Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; body 10 ...
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... TD[2:1] ACCEPTANCE FILTERS (1) Shared with GPIO. (2) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (3) Only 1 for LPC2109. (4) SSP interface and high-speed GPIO are available on LPC2109/01, LPC2119/01, and LPC2129/01 only. Fig 1. Block diagram LPC2109_2119_2129_6 Product data sheet (2) (2) TMS ...
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... No TD2 and RD2 for LPC2109. (2) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 2. Pin configuration LPC2109_2119_2129_6 Product data sheet LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers LPC2109 LPC2119 (2) LPC2129 Rev. 06 — 10 December 2007 www.DataSheet4U.com 48 P1[20]/TRACESYNC 47 P0[17]/CAP1[2]/SCK1/MAT1[2] 46 P0[16]/EINT0/MAT0[2]/CAP0[2] 45 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin Type Description P0[0] to P0[31] I/O P0[0]/TXD0 PWM1 O P0[1]/RXD0 PWM3/EINT0 O I P0[2]/SCL/ 22 I/O CAP0[0] I P0[3]/SDA/ 26 I/O MAT0[0]/EINT1 O I P0[4]/SCK0/ 27 I/O CAP0[1] I P0[5]/MISO0/ 29 I/O MAT0[1] O P0[6]/MOSI0/ 30 I/O CAP0[2] I P0[7]/SSEL0 PWM2/EINT2 O I P0[8]/TXD1 PWM4 O P0[9]/RXD1 PWM6/EINT3 O I P0[10]/RTS1/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type Description P0[15]/RI1/EINT2 P0[16]/EINT0 MAT0[2]/CAP0[ P0[17]/CAP1[2 SCK1/MAT1[2] I/O O P0[18]/CAP1[3 MISO1/MAT1[3] I/O O P0[19]/MAT1[2 MOSI1/CAP1[2] I/O I P0[20]/MAT1[3 SSEL1/EINT3 I I P0[21]/PWM5 CAP1[3] I P0[22]/CAP0[0 MAT0[0] O P0[23]/RD2 3 I P0[24]/TD2 5 O P0[25]/RD1 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type Description P1[16 TRACEPKT0 P1[17 TRACEPKT1 P1[18 TRACEPKT2 P1[19 TRACEPKT3 P1[20 TRACESYNC P1[21 PIPESTAT0 P1[22 PIPESTAT1 P1[23 PIPESTAT2 P1[24 TRACECLK P1[25]/EXTIN0 28 I P1[26]/RTCK 24 I/O P1[27]/TDO 64 O P1[28]/TDI 60 I P1[29]/TCK 56 I P1[30]/TMS 52 I P1[31]/TRST 20 I TD1 ...
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... DD(3V3 DDA(3V3) [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. LPC2109_2119_2129_6 Product data sheet Analog 1.8 V core power supply; this is the power supply voltage for internal circuitry. This should be nominally the same voltage as V isolated to minimize noise and error. 3.3 V pad power supply; this is the power supply voltage for the I/O ports. ...
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... NXP Semiconductors 6. Functional description Details of the LPC2109/2119/2129 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit. The LPC2109/2119/2129 provide static RAM for the LPC2109 and 16 kB for the LPC2119 and LPC2129. 6.4 Memory map The LPC2109/2119/2129 memory maps incorporate several distinct regions, as shown in Figure 3 ...
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... BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY) RESERVED ADDRESS SPACE 16 kB ON-CHIP STATIC RAM (LPC2119/2129 ON-CHIP STATIC RAM (LPC2109) 1.0 GB RESERVED ADDRESS SPACE 256 kB ON-CHIP FLASH MEMORY (LPC2129) 128 kB ON-CHIP FLASH MEMORY (LPC2119 ON-CHIP FLASH MEMORY (LPC2109) 0.0 GB Rev. 06 — 10 December 2007 www.DataSheet4U.com LPC2109/2119/2129 ...
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... NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. ...
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... System Control ADC CAN [1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled ...
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... The ADC pads are 5 V tolerant when configured for digital I/O function(s). 6.9 CAN controllers and acceptance filter The LPC2119 and LPC2129 each contain two CAN controllers, while the LPC2109 has one CAN controller. The CAN is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security ...
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... NXP Semiconductors • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.10.2 UART features available in LPC2109/2119/2129/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
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... NXP Semiconductors 6.12 SPI serial I/O controller The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
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... NXP Semiconductors to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. 6.14.1 Features • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. ...
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... NXP Semiconductors • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T cy(PCLK) 6.16 Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected ...
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... NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specifi ...
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... NXP Semiconductors 6.18.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU) ...
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... NXP Semiconductors CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. ...
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... NXP Semiconductors 6.18.8 APB The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB so that they can operate at the speed chosen for the ARM processor ...
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... NXP Semiconductors pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current SS T junction temperature ...
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... OL I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu Power consumption LPC2109/00, LPC2119, LPC2119/00, LPC2129, LPC2129/00 I active mode supply DD(act) current I Power-down mode supply DD(pd) current LPC2109_2119_2129_6 Product data sheet Conditions [2] [ pull-up ...
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... NXP Semiconductors Table 6. Static characteristics …continued +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Power consumption LPC2109/01, LPC2119/01, LPC2129/01 I active mode supply DD(act) current I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins ...
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... NXP Semiconductors Table 7. ADC static characteristics 3.6 V unless otherwise specified; T DDA 4.5 MHz. Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral non-linearity L(adj) E offset error O E gain error G E absolute error T [1] Conditions 3.3 V. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 8.1 Power consumption measurements for LPC2109/01, LPC2119/01, LPC2129/01 devices The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
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... NXP Semiconductors 10 I DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 7. Typical LPC2109/01 I DD(idle DD(idle) (mA) 7.5 5.0 2.5 0 1.65 1.70 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 10. Typical LPC2119/01 and LPC2129/01 I LPC2109_2119_2129_6 Product data sheet all peripherals enabled all peripherals disabled 28 36 measured at different frequencies DD(act) 60 MHz ...
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... Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 12. Typical LPC2119/01 and LPC2129/01 I LPC2109_2119_2129_6 Product data sheet all peripherals enabled all peripherals disabled 28 36 measured at different frequencies DD(idle) 60 MHz ...
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... I DD(idle) (mA 1.65 1.70 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 14. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I LPC2109_2119_2129_6 Product data sheet LPC2109/2119/2129 60 MHz 48 MHz 12 MHz 1.75 1.80 1.85 measured at different voltages DD(act) 60 MHz ...
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... DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 16. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I LPC2109_2119_2129_6 Product data sheet LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers 60 MHz 48 MHz 12 MHz 10 35 CCLK measured at different temperatures ...
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... NXP Semiconductors 200 I DD(pd 160 120 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 17. Typical LPC2109/01, LPC2119/01, and LPC2129/01 core power-down current I temperatures Table 8. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 ...
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... NXP Semiconductors Table 9. Core voltage 1 Peripheral RTC ADC CAN1/2 LPC2109_2119_2129_6 Product data sheet Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active mode …continued = 25 C; all measurements in A; PCLK = amb CCLK = 12 MHz 16 33 229 Rev. 06 — 10 December 2007 www.DataSheet4U.com LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers CCLK ...
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... NXP Semiconductors 9. Dynamic characteristics Table 10. Dynamic characteristics +85 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL ...
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... NXP Semiconductors 9.1 Timing V DD Fig 18. External clock timing LPC2109_2119_2129_6 Product data sheet 0.5 V 0.2V 0 0. CHCL Rev. 06 — 10 December 2007 www.DataSheet4U.com LPC2109/2119/2129 Single-chip 16/32-bit microcontrollers t CHCX t t CLCX CLCH T cy(clk) 002aaa907 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 11. Acronym ADC AMBA APB CAN CPU DCC FIFO GPIO I/O PLL PWM RAM SPI SRAM SSI SSP TTL UART LPC2109_2119_2129_6 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Controller Area Network ...
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... Type number LPC2109FBD64/01 has been added. • Type number LPC2119FBD64/01 has been added. • Type number LPC2129FBD64/01 has been added. • Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) have been added. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19 Emulation and debugging 6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19.2 Embedded trace macrocell . . . . . . . . . . . . . . 23 6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Static characteristics . . . . . . . . . . . . . . . . . . . 26 8.1 Power consumption measurements for LPC2109/01, LPC2119/01, LPC2129/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 38 9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 13 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 13.2 Defi ...