LPC2158 NXP Semiconductors, LPC2158 Datasheet
LPC2158
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LPC2158 Summary of contents
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... MHz operation on-chip static RAM and 512 kB of on-chip flash memory. I USB 2.0 Full-speed compliant device controller with endpoint RAM additional on-chip RAM accessible to USB by DMA (LPC2158 only segment I Single 10-bit DAC provides variable analog output. I Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input ...
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... NXP Semiconductors 4. Block diagram P0[31:28], P0[27:26] P0[25], P0[23:0] (1) LPC2157 only. Fig 1. Block diagram of LPC2157/2158 LPC2157_2158_2 Product data sheet P1[31:25], P1[17:16] LPC2157/ LPC2158 (1) , MCU Rev. 02 — 9 February 2009 www.DataSheet4U.com LPC2157/2158 Single-chip 16-bit/32-bit microcontrollers PCF8576D LCD CONTROLLER 002aad382 © NXP B.V. 2009. All rights reserved. S[31:0] BP[3:0] V LCD ...
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... AND 1 AD1[7:0] AOUT P0[31:28] and GENERAL P0[25:0] PURPOSE I/O P1[31:16] PWM[6:1] PWM0 (1) Pins shared with GPIO. (2) USB DMA controller with RAM accessible as general purpose RAM and/or DMA is available in LPC2158 only. (3) LPC2157 only. Fig 2. Microcontroller section block diagram LPC2157_2158_2 Product data sheet (1) (1) TMS TDI (1) ...
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... NXP Semiconductors V DD(LCD) LCD BIAS GENERATOR V LCD CLK TIMING SYNC OSCILLATOR OSC V SS SCL_LCD INPUT FILTERS SDA_LCD Fig 3. LCD display controller block diagram 5. Pinning information 5.1 Pinning Fig 4. Pin configuration for LPC2157 LPC2157_2158_2 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE ...
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... NXP Semiconductors Fig 5. Pin configuration for LPC2158 5.2 Pin description Table 2. Pin description LPC2157 Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/TXD0/ 7 I/O PWM1 O O [2] P0[1]/RXD0/ 9 I/O PWM3/EINT0 [3] P0[2]/SCL0/ 10 I/O CAP0[0] I/O I [3] P0[3]/SDA0/ 14 I/O MAT0[0]/EINT1 I [4] P0[4]/SCK0/ 15 I/O CAP0[1]/AD0[6] I [4] P0[5]/MISO0/ 17 I/O MAT0[1]/AD0[7] I LPC2157_2158_2 ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin Type [4] P0[6]/MOSI0/ 18 I/O CAP0[2]/AD1[0] I [2] P0[7]/SSEL0/ 19 I/O PWM2/EINT2 [4] P0[8]/TXD1/ 20 I/O PWM4/AD1[ [2] P0[9]/RXD1/ 21 I/O PWM6/EINT3 [4] P0[10]/RTS1/ 22 I/O CAP1[0]/AD1[ [3] P0[11]/CTS1/ 23 I/O CAP1[1]/SCL1 I I I/O [4] P0[12]/DSR1/ 24 I/O MAT1[0]/AD1[ [4] P0[13]/DTR1/ 25 I/O MAT1[1]/AD1[4] ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin Type [4] P0[15]/RI1/ 28 I/O EINT2/AD1[ [2] P0[16]/EINT0/ 29 I/O MAT0[2]/CAP0[ [1] P0[17]/CAP1[2]/ 30 I/O SCK1/MAT1[2] I I/O O [1] P0[18]/CAP1[3]/ 79 I/O MISO1/MAT1[3] I I/O O [1] P0[19]/MAT1[2]/ 80 I/O MOSI1/CAP1[2] O I/O I [2] P0[20]/MAT1[3]/ 81 I/O SSEL1/EINT3 [4] P0[21]/PWM5/ 91 I/O AD1[6]/CAP1[ [4] P0[22]/AD1[7]/ 92 I/O CAP0[0]/ I MAT0[ [1] P0[23] 84 ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin Type [7] P0[27]/AD0[0]/ 99 I/O CAP0[1]/MAT0[ [4] P0[28]/AD0[1]/ 1 I/O CAP0[2]/MAT0[ [4] P0[29]/AD0[2]/ 2 I/O CAP0[3]MAT0[ [4] P0[30]/AD0[3]/ 3 I/O EINT3/CAP0[ [6] P0[31 P1[0] to P1[31] I/O [6] P1[16] 4 I/O [6] P1[17] 100 I/O [6] P1[25]/EXTIN0 16 I/O I [6] P1[26]/RTCK 12 I/O I/O [6] P1[27]/TDO 90 I/O O [6] P1[28]/TDI 86 I/O I [6] P1[29]/TCK ...
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... NXP Semiconductors Table 2. Pin description LPC2157 Symbol Pin Type [8] RESET 83 I [9] XTAL1 88 O [9] XTAL2 87 I [9] RTCX1 93 I [9] RTCX2 13, 32 39, 40, 85 11, 27 DDA DD(LCD LCD VREF 89 I VBAT 31 I SDA_LCD 34 I/O SCL_LCD 35 I SYNC ...
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... NXP Semiconductors Table 3. Pin description LPC2158 Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/TXD0/ 7 I/O PWM1 O O [2] P0[1]/RXD0/ 9 I/O PWM3/EINT0 [3] P0[2]/SCL0/ 10 I/O CAP0[0] I/O I [3] P0[3]/SDA0/ 14 I/O MAT0[0]/EINT1 I [4] P0[4]/SCK0/ 15 I/O CAP0[1]/AD0[6] I [4] P0[5]/MISO0/ 17 I/O MAT0[1]/AD0[7] I [4] P0[6]/MOSI0/ 18 I/O CAP0[2]/AD1[0] I [2] P0[7]/SSEL0/ 19 I/O PWM2/EINT2 [4] P0[8]/TXD1/ ...
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... NXP Semiconductors Table 3. Pin description LPC2158 Symbol Pin Type [2] P0[9]/RXD1/ 21 I/O PWM6/EINT3 [4] P0[10]/RTS1/ 22 I/O CAP1[0]/AD1[ [3] P0[11]/CTS1/ 23 I/O CAP1[1]/SCL1 I I I/O [4] P0[12]/DSR1/ 24 I/O MAT1[0]/AD1[ [4] P0[13]/DTR1/ 25 I/O MAT1[1]/AD1[ [3] P0[14]/DCD1/ 26 I/O EINT1/SDA1 I I I/O [4] P0[15]/RI1/ 28 I/O EINT2/AD1[ [2] P0[16]/EINT0/ 29 I/O MAT0[2]/CAP0[2] ...
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... NXP Semiconductors Table 3. Pin description LPC2158 Symbol Pin Type [1] P0[18]/CAP1[3]/ 79 I/O MISO1/MAT1[3] I I/O O [1] P0[19]/MAT1[2]/ 80 I/O MOSI1/CAP1[2] O I/O I [2] P0[20]/MAT1[3]/ 81 I/O SSEL1/EINT3 [4] P0[21]/PWM5/ 91 I/O AD1[6]/CAP1[ [4] P0[22]/AD1[7]/ 92 I/O CAP0[0]/ I MAT0[ [1] P0[23]/V 84 I/O BUS I [5] P0[25]/AD0[4]/ 97 I/O AOUT I O [4] P0[28]/AD0[1]/ 1 I/O CAP0[2]/MAT0[ [4] P0[29]/AD0[2]/ 2 I/O CAP0[3]/MAT0[3] ...
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... NXP Semiconductors Table 3. Pin description LPC2158 Symbol Pin Type [6] P0[31]/UP_LED CONNECT O O P1[0] to P1[31] I/O [6] P1[16] 4 I/O [6] P1[17] 100 I/O [6] P1[25]/EXTIN0 16 I/O I [6] P1[26]/RTCK 12 I/O I/O [6] P1[27]/TDO 90 I/O O [6] P1[28]/TDI 86 I/O I [6] P1[29]/TCK 82 I/O I [6] P1[30]/TMS 78 I/O I [6] P1[31]/TRST 8 I I/O [ I/O [8] RESET 83 I [9] XTAL1 88 O [9] XTAL2 87 I [9] RTCX1 93 I [9] ...
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... NXP Semiconductors Table 3. Pin description LPC2158 Symbol Pin Type V 11, 27 DDA DD(LCD LCD VREF 89 I VBAT 31 I SDA_LCD 34 I/O SCL_LCD 35 I SYNC 36 I/O CLK 37 I/O BP0 to BP3 S31 [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC) ...
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... NXP Semiconductors In case of LPC2158 only SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution. 6.4 Memory map The LPC2157/2158 memory map incorporates several distinct regions, as shown in Figure 6 ...
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... NXP Semiconductors FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifi ...
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... All I/O default to inputs after reset. 6.8 10-bit ADC The LPC2157/2158 contain two single 10-bit successive approximation ADCs. While ADC0 has eight channels (six channels for LPC2158), ADC1 has eight channels. Therefore, the total number of available ADC inputs for LPC2157 is 16 and for LPC2158 is 14. 6.8.1 Features • ...
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... NXP Semiconductors The LPC2158 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers ...
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... NXP Semiconductors 2 6.12 I C-bus serial I/O controller The LPC2157/2158 each contain two I 2 The I C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)) ...
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... NXP Semiconductors slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data ...
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... NXP Semiconductors 6.16 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. ...
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... NXP Semiconductors Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs ...
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... NXP Semiconductors 6.19 System control 6.19.1 Crystal oscillator On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called f referred to as CCLK for purposes of rate equations, etc. f unless the PLL is running and connected. Refer to information. 6.19.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO) ...
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... NXP Semiconductors 6.19.4 Brownout detector The LPC2157/2158 include 2-stage monitoring of the voltage on the V voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low voltage detection asserts reset to inactivate the LPC2157/2158 when the voltage on the V fl ...
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... NXP Semiconductors In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specifi ...
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... NXP Semiconductors The JTAG clock (TCK) must be slower than interface to operate. 6.20.2 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2157/2158 contain a specifi ...
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... NXP Semiconductors 6.21.4 Oscillator 6.21.4.1 Internal clock An internal oscillator provides the clock signals for the internal logic of the LCD controller and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the clock starts. 6.21.5 Timing The LCD controller timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs ...
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... NXP Semiconductors 6.21.11 Output bank selector The LCD controller includes a RAM bank switching feature in the static and 1:2 drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit selected for display instead of the contents of bit 0. In 1:2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1 ...
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... NXP Semiconductors 2 6.21.15 I C-bus slave addresses 2 The I C-bus slave address is 0111 0000. The LCD controller is a write-only device and will not respond to a read access. LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 02 — 9 February 2009 www.DataSheet4U.com LPC2157/2158 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 7. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF i(VREF) V analog input voltage ...
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... NXP Semiconductors 8. Static characteristics Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage DD V analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin i(VREF) VREF Standard port pins, RESET, RTCK ...
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... NXP Semiconductors Table 7. Static characteristics …continued +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode supply DD(act) current I Power-down mode DD(pd) supply current I Power-down mode BATpd battery supply current I active mode battery BATact supply current I optimized active mode ...
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... NXP Semiconductors Table 7. Static characteristics …continued +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 USB pins I OFF-state output OZ current V bus supply voltage ...
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... NXP Semiconductors Table 8. ADC static characteristics +85 C unless otherwise specified; ADC frequency 4.5 MHz. DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors ADx[y] SAMPLE Fig 8. Suggested ADC interface - LPC2157/2158 ADx[y] pin LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers LPC2XXX R vsi 20 k ADx[ Rev. 02 — 9 February 2009 www.DataSheet4U.com LPC2157/2158 V EXT 002aad458 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 9. Dynamic characteristics Table 9. Dynamic characteristics of USB pins (full-speed pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... Fig 10. Differential data-to-EOP transition skew and EOP width 10. Application information 10.1 Suggested USB interface solutions LPC2158 Fig 11. LPC2158 USB interface using the CONNECT function on pin 17 LPC2157_2158_2 Product data sheet t t CHCL CLCX T cy(clk) ...
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... NXP Semiconductors LPC2158 Fig 12. LPC2158 USB interface using the UP_LED function on pin 17 LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers 1.5 k UP_LED VBUS 002aad411 Rev. 02 — 9 February 2009 www.DataSheet4U.com LPC2157/2158 USB-B connector © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 11. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Abbreviations Table 11. Acronym ADC AHB AMBA APB BOD DAC DCC DMA FIFO GPIO I/O ISP JTAG MCU PLL POR PWM RC SPI SSI SSP TTL UART LPC2157_2158_2 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture ...
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... NXP Semiconductors 13. Revision history Table 12. Revision history Document ID Release date LPC2157_2158_2 20090209 • Modifications: Section 2 • Section 2 • Section 5.2 “Pin • Section 6.20.1 • Table 7 “Static • Table 7 “Static LPC2157_2158_1 20081015 LPC2157_2158_2 Product data sheet Single-chip 16-bit/32-bit microcontrollers Data sheet status ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... Memory map 6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 16 6.5.1 Interrupt sources 6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17 6.7 Fast general purpose parallel I 6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.10 USB 2.0 device controller (LPC2158 only 6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 6.12 I C-bus serial I/O controller . . . . . . . . . . . . . . 20 6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.13 SPI serial I/O controller 6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.14 SSP serial I/O controller . . . . . . . . . . . . . . . . . 20 6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 ...