LPC2929 NXP Semiconductors, LPC2929 Datasheet
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LPC2929 Summary of contents
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LPC2927/2929 ARM9 microcontroller with CAN, LIN, and USB Rev. 02 — 22 June 2009 1. General description The LPC2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...
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... NXP Semiconductors I Other peripherals: N One 10-bit ADC with 5.0 V measurement range and eight input channels with conversion times as low as 2.44 s per channel. N Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an additional 16 analog inputs with conversion times as low as 2.44 s per channel. Each channel provides a compare function to minimize interrupts. ...
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... LPC2929FBD144 768 kB [1] Note that parts LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917, LPC2919 and LPC2917/01, LPC2919/01. The MSCSS and timer blocks have a reduced pinout on the LPC2927/29. LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors 4. Block diagram LPC2927/2929 VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT TIMER0/1 MTMR PWM0/1/2/3 3.3 V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 networking subsystem GLOBAL ACCEPTANCE FILTER UART/LIN0/1 I2C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. ...
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... V power supply for I/O DD(IO) [1] P2[22]/SCK2/ 10 GPIO 2, pin 22 PCAP2[2]/D20 LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB 1 108 LPC2927FBD144 LPC2929FBD144 36 73 002aae144 Function 1 Function 2 SPI2 SDI PWM2 CAP1 UART1 TXD CAN1 TXD UART1 RXD CAN1 RXD - UART1 TXD ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default) [1] P2[23]/SCS1[0]/ 11 GPIO 2, pin 23 PCAP3[0]/D21 [1] P3[6]/SCS0[3]/ 12 GPIO 3, pin 6 PMAT1[0]/TXDL1 [1] P3[7]/SCS2[1]/ 13 GPIO 3, pin 7 PMAT1[1]/RXDL1 [1] P0[30]/CAP0[2]/ 14 GPIO 0, pin 30 MAT0[2] [1] P0[31]/CAP0[3]/ 15 GPIO 0, pin 31 MAT0[3] [1] P2[24]/SCS1[1]/ 16 GPIO 2, pin 24 PCAP3[1]/D22 [1] P2[25]/SCS1[2]/ ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default) [1] P1[22]/TXD0/ 35 GPIO 1, pin 22 USB_UP_LED/ CS4 [1] TMS 36 IEEE 1149.1 test mode select, pulled up internally [1] TCK 37 IEEE 1149.1 test clock [1] P1[21]/CAP3[3]/ 38 GPIO 1, pin 21 CAP1[3]/D7 [1] P1[20]/CAP3[2]/ 39 GPIO 1, pin 20 SCS0[1]/D6 [1] P1[19]/CAP3[1]/ 40 GPIO 1, pin 19 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default ground for digital core SS(CORE 1.8 V power supply for digital core DD(CORE) [1] P3[13]/SDO1/ 61 GPIO 3, pin 13 EI5/IDX0 [1] P2[4]/MAT1[0]/ 62 GPIO 2, pin 4 EI0/D12 [1] P2[5]/MAT1[1]/ 63 GPIO 2, pin 5 EI1/D13 [1] P1[9]/SDO1/ 64 GPIO 1, pin 9 RXDL1/CS1 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default) [1] P1[3]/SCS2[1]/ 85 GPIO 1, pin 3 PMAT3[3]/A3 [1] P1[2]/SCS2[3]/ 86 GPIO 1, pin 2 PMAT3[2]/A2 [1] P1[1]/EI1/ 87 GPIO 1, pin 1 PMAT3[1]/ ground for digital core SS(CORE 1.8 V power supply for digital core DD(CORE) [1] P1[0]/EI0/ 90 GPIO 1, pin 0 PMAT3[0]/A0 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default) V 109 5 V supply voltage for ADC0 and 5 V reference for ADC0. DDA(ADC5V0) [3] VREFP 110 HIGH reference for ADC [3] VREFN 111 LOW reference for ADC [4] P0[8]/IN1[0]/TXDL0/ 112 GPIO 0, pin 8 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin Description Function 0 (default) [4] P0[19]/IN2[3]/ 133 GPIO 0, pin 19 PMAT2[1]/A15 [1] P3[4]/MAT3[2]/ 134 GPIO 3, pin 4 PMAT2[4]/TXDC1 [1] P3[5]/MAT3[3]/ 135 GPIO 3, pin 5 PMAT2[5]/RXDC1 [1] P2[18]/SCS2[1]/ 136 GPIO 2, pin 18 PCAP1[1]/D16 [1] P2[19]/SCS2[0]/ 137 GPIO 2, pin 19 PCAP1[2]/D17 ...
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... NXP Semiconductors The LPC2927/2929 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place ...
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... NXP Semiconductors 6.3 On-chip flash memory system The LPC2927/2929 includes a 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated on the LPC2927/2929 ...
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Memory map LPC2927/2929 0xFFFF FFFF VIC 0xFFFF F000 reserved PCR/VIC 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature ...
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... NXP Semiconductors 6.6 Reset, debug, test, and power description 6.6.1 Reset and power-up behavior The LPC2927/2929 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See Section 9 the reset pin. ...
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... NXP Semiconductors 6.6.3.1 ETM/ETB The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace buffer. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand. The ETB stores trace data produced by the ETM ...
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... NXP Semiconductors Two of the base clocks generated by the CGU0 are used as input into a second, dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate two base clocks for the USB controller and one base clock for an independent clock output. ...
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... NXP Semiconductors specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should not be switched off. See for more details of how to control the individual branch clocks. Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK ...
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... NXP Semiconductors Table 7. Base clock BASE_MSCSS_CLK BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK reserved BASE_ICLK1_CLK [1] This clock is always on (cannot be switched off for system safety reasons). [2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock source. See ...
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... NXP Semiconductors 6.8 Flash memory controller The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the bootloader. Flash memory contents can be protected by disabling JTAG access. Suspension of burning or erasing is not supported. The Flash Memory Controller (FMC) interfaces to the embedded fl ...
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... NXP Semiconductors When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer primary buffer, hit data can be copied to the secondary buffer line, which allows the fl ...
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... NXP Semiconductors Table 10 gives an overview of the flash-sector base addresses. Table 10. Sector number [1] 7 [1] 8 [1] 9 [1] 10 [1] Availability of sector 7 to sector 10 depends on device type, see The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular fl ...
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... NXP Semiconductors Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. 6.8.6 EEPROM EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the fl ...
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... NXP Semiconductors Table 11. 32-bit system address bit field and Table 12. CS[2:0] 000 001 010 011 100 101 110 111 6.9.2 Pin description The external static-memory controller module in the LPC2927/2929 has the following pins, which are combined with other functions on the port pins of the LPC2927/2929. ...
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... NXP Semiconductors WSTOEN = 3, WST1 = 6 Fig 5. Reading from external memory A timing diagram for writing to external memory is shown In between wait-state settings is indicated with arrows. WSTWEN = 3, WST2 = 7 (1) BLS has the same timing configurations that use the byte lane enable signals to connect to write enable (8 bit devices) ...
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... NXP Semiconductors Usage of the idle/turn-around time (IDCY) is demonstrated In are added between a read and a write cycle in the same external memory device. CLK(SYS WSTOEN = 2, WSTWEN = 4, WST1 = 6, WST2 = 4, IDCY = 5 Fig 7. Reading/writing external memory Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function ...
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... NXP Semiconductors 6.10.2 Clock description The GPDMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see Section 6.7.2. 6.11 USB interface The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic confi ...
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... NXP Semiconductors The USB OTG controller has the following features: • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a . • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). ...
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... NXP Semiconductors 6.12 General subsystem 6.12.1 General subsystem clock description The general subsystem is clocked by CLK_SYS_GESS, see 6.12.2 Chip and feature identification The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains identify the silicon and also registers containing information about the features enabled or disabled on the chip ...
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... NXP Semiconductors 6.12.4.1 Pin description The event router module in the LPC2927/2929 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2927/2929. shows the pins connected to the event router. Table 15. Symbol EXTINT CAN0 RXD CAN1 RXD ...
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... NXP Semiconductors • Debug mode with disabling of reset • Watchdog control register change-protected with key • Programmable 32-bit watchdog timer period with programmable 32-bit prescaler. 6.13.2.1 Functional description The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted ...
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... NXP Semiconductors – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match • Pause input pin (MSCSS timers only) The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. They also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt ...
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... NXP Semiconductors • 16-byte receive and transmit FIFOs. • Register locations conform to 550 industry standard. • Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes. • Built-in baud rate generator. • Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode ...
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... NXP Semiconductors • Serial clock-rate slave mode: fserial_clk = f • Internal loopback test mode. The SPI module can operate in: • Master mode: – Normal transmission mode – Sequential slave mode • Slave mode 6.13.5.1 Functional description The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces ...
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... NXP Semiconductors 6.13.5.3 Clock description The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx ( 2), see power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS ...
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... NXP Semiconductors 6.13.6.3 Clock description The GPIO modules are clocked by several clocks, all of which are derived from BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx ( 5), see Section 6.7.2. Note that each GPIO has its own CLK_SYS_GPIOx branch clock for power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK ...
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... NXP Semiconductors 6.14.2 LIN The LPC2927/2929 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2.0 master controllers with additional support for sync break generation and with hardware implementation of the LIN protocol according to spec 2.0. Remark: Both LIN channels can be also configured as UART channels. ...
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... NXP Semiconductors • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ...
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... NXP Semiconductors The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. Capture inputs are provided to measure event phases compared to the main counter. Depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. ...
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... NXP Semiconductors MSCSS MSCSS TIMER0 MSCSS PAUSE TIMER1 Fig 8. Modulation and sampling control subsystem (MSCSS) block diagram LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB AHB-TO-APB BRIDGE QEI ADC0 start synch start ADC1 start synch start ADC2 ...
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... NXP Semiconductors 6.15.2 Pin description The pins of the LPC2927/2929 MSCSS associated with the three ADC modules are described in Section 6.15.5.4, pins directly connected to the MSCSS timer 1 module are described in Section 6.15.6.1, and pins connected to the quadrature encoder interface are described in Section 6.15.7.1. 6.15.3 Clock description The MSCSS is clocked from a number of different sources: • ...
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... NXP Semiconductors 6.15.4.1 Functional description The ADC block diagram, functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain. A mechanism is provided to modify confi ...
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... NXP Semiconductors Table 23. Symbol ADC0 IN[7:0] ADC1/2 IN[7:0] ADC2_EXT_START CAP1[2] VREFN VREFP V DDA(ADC5V0) V DDA(ADC3V3) [1] VREFP, VREFN, V [2] The analog inputs of ADC0 are internally multiplied by a factor of 3 3.3 V, the maximum digital result is 1024 3.3/ 5. [3] V DDA(ADC5V0) Remark: The following formula only applies to ADC0: Voltage variations on VREFP (i.e. those that deviate from voltage variations on the ...
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... NXP Semiconductors 6.15.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2927/2929 includes four PWM modules with the following features. • Six pulse-width modulated output signals • Double edge features (rising and falling edges programmed individually) • Optional interrupt generation on match (each edge) • ...
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... NXP Semiconductors APB system bus CONTROL IRQ pwm REGISTERS IRQ capt_match Fig 10. PWM block diagram The PWM block diagram in functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective ...
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... NXP Semiconductors 6.15.5.3 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted ...
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... NXP Semiconductors 6.15.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2927/2929. timer 1 external pin. Table 25. Symbol MSCSS PAUSE 6.15.6.2 Clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx ( 1), see Section 6 ...
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... NXP Semiconductors 6.15.7.1 Pin description The QEI module in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2927/2929. Table 26. Symbol QEI0 IDX QEI0 PHA QEI0 PHB 6.15.7.2 Clock description The QEI module is clocked by CLK_MSCSS_QEI, see this clock is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK ...
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... NXP Semiconductors EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU0 REGISTERS AHB2DTL BRIDGE RGU REGISTERS POR reset from watchdog counter RST (device pin) Fig 11. PCRSS block diagram 6.16.1 Clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes ...
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... NXP Semiconductors 6.16.2 Clock Generation Unit (CGU0) The key features are: • Generation of 11 base clocks, selectable from several embedded clock sources. • Crystal oscillator with power-down. • Control PLL with power-down. • Very low-power ring oscillator, always on to provide a safe clock. ...
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... NXP Semiconductors CLOCK GENERATION UNIT (CGU0) 400 kHz LP_OSC clkout clkout120 EXTERNAL PLL OSCILLATOR clkout240 FREQUENCY MONITOR Fig 12. Block diagram of the CGU0 (see There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU0 itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer) ...
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... NXP Semiconductors Configuration of the CGU0: choice can be made from the primary and secondary clock generators according to Figure 13. Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0: one of the outputs of the PLL or to LP_OSC/crystal oscillator directly ...
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... NXP Semiconductors generator. The RDET register keeps track of which clocks are active and inactive, and the appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notifi change in internal clock status. ...
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... NXP Semiconductors Triple output phases: clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120 phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown ...
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... NXP Semiconductors CLOCK GENERATION UNIT clkout BASE_ICLK0_CLK clkout120 PLL clkout240 BASE_ICLK1_CLK Fig 15. Block diagram of the CGU1 6.16.3.1 Pin description The CGU1 module in the LPC2927/2929 has the pins listed in Table 29. Symbol CLK_OUT 6.16.4 Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: • ...
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... NXP Semiconductors 6.16.4.1 Functional description Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see table form a sort of cascade to provide the multiple levels of impact that a reset may have. The combined input sources are logically OR-ed together so that activating any of the listed reset sources causes the output to go active ...
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... NXP Semiconductors Table 31. Symbol RST 6.16.5 Power Management Unit (PMU) This module enables software to actively control the system’s power consumption by disabling clocks not required in a particular operating mode. Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2927/2929 ...
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... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors 6.17.1 Functional description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: • Target 0 is ARM processor FIQ (fast interrupt service). ...
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... NXP Semiconductors 7. Limiting values Table 33. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Supply pins P total power dissipation tot V core supply voltage DD(CORE) V oscillator and PLL supply DD(OSC_PLL) voltage V 3.3 V ADC analog supply DDA(ADC3V3) voltage V 5.0 V ADC analog supply ...
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... NXP Semiconductors Table 33. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD V electrostatic discharge ESD voltage [1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximum input voltage is defined by V ...
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... NXP Semiconductors 8. Static characteristics Table 34. Static characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter Supplies Core supply V core supply voltage DD(CORE) ...
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... NXP Semiconductors Table 34. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter V LOW-level input voltage IL V hysteresis voltage hys I HIGH-level input leakage ...
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... NXP Semiconductors Table 34. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter I LOW-level output current OL I HIGH-level short-circuit OHS output current ...
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... NXP Semiconductors Table 35. ADC static characteristics +85 C unless otherwise specified; ADC frequency 4.5 MHz. DDA(ADC3V3) amb Symbol Parameter V voltage on pin VREFN VREFN V voltage on pin VREFP VREFP V analog input voltage IA Z input impedance i C analog input capacitance ia E differential linearity error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 8.1 Power consumption 80 I DD(CORE) (mA Conditions: T peripherals enabled but not configured to run. Fig 18 DD(CORE) (mA Conditions: T but not configured to run. Fig 19. I LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors 80 I DD(CORE) (mA Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 20. 8.2 Electrical pin characteristics 500 V OL (mV) 400 300 200 100 V Fig 21. Typical LOW-level output voltage versus LOW-level output current ...
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... NXP Semiconductors 3 (V) 3.0 2.5 2.0 V Fig 22. Typical HIGH-level output voltage versus HIGH-level output current 80 I I(pd Fig 23. Typical pull-down current versus temperature LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB 1.0 2.0 3.0 = 3.3 V. DD(IO 3 Rev. 02 — 22 June 2009 www ...
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... NXP Semiconductors 20 I I(pu 100 V Fig 24. Typical pull-up current versus temperature LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO Rev. 02 — 22 June 2009 www.DataSheet4U.com LPC2927/2929 002aae692 = 2.7 V 3 temperature ( C) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9. Dynamic characteristics 9.1 Dynamic characteristics: I/O and CLKOUT pins, internal clock, oscillators, PLL, and CAN Table 36. Dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I/O pins t HIGH to LOW transition THL time ...
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... NXP Semiconductors 520 f ref(RO) (kHz) 510 500 490 480 Fig 25. Low-power ring oscillator thermal characteristics LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB Rev. 02 — 22 June 2009 www.DataSheet4U.com LPC2927/2929 002aae373 1.9 V 1 temperature ( C) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9.2 USB interface Table 37. Dynamic characteristics: USB pins (full-speed pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 9.3 Dynamic characteristics: I Table 38. Dynamic characteristic 2 3 DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified Symbol Parameter t output fall time f(o) [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level. Cased products are tested at T test conditions to cover the specifi ...
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... NXP Semiconductors 9.4 Dynamic characteristics: SPI Table 39. Dynamic characteristics of SPI pins 2 3 DD(CORE) DD(OSC_PLL) DD(IO - +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter f SPI operating frequency SPI ...
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... NXP Semiconductors 9.5 Dynamic characteristics: flash memory and EEPROM Table amb V DDA(ADC3V3) Symbol N endu t ret t prog init t wr(pg) t fl(BIST) t a(clk) t a(A) [1] Number of program/erase cycles. Table amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2927_29_2 ...
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... NXP Semiconductors 9.6 Dynamic characteristics: external static memory Table 42. External static memory interface dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter T clock cycle time CLCL t internal read access time a(R)int t internal write access time a(W)int Read cycle parameters t CS LOW to address valid ...
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... NXP Semiconductors CSLOEL OE/BLS Fig 28. External memory read access CS BLS Fig 29. External memory write access LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t t CSLWEL ...
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... NXP Semiconductors 9.7 Dynamic characteristics: ADC Table 43. ADC dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter 5.0 V ADC0 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time conv 3.3 V ADC1/2 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time conv [1] All parameters are guaranteed over the virtual junction temperature range by design ...
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... NXP Semiconductors 145 core frequency (MHz) 135 125 115 105 Fig 30. Core operating frequency versus temperature for different core voltages. 145 core frequency (MHz) 135 125 115 105 Fig 31. Core operating frequency versus core voltage for different temperatures LPC2927_29_2 Preliminary data sheet ...
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... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2927/2929 USB interface on a self-powered device LPC29xx Fig 33. LPC2927/2929 USB interface on a bus-powered device LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 k USB_VBUS USB_D+ ...
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... NXP Semiconductors USB_RST LPC29xx USB_SCL USB_SDA USB_INT USB_D+ USB_D Fig 34. LPC2927/2929 USB OTG port configuration USB_UP_LED USB_CONNECT LPC29xx USB_D+ USB_D USB_VBUS Fig 35. LPC2927/2929 USB device port configuration LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) R1 ...
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... NXP Semiconductors 10.3 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 36. SPI timing in master mode SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 37. SPI timing in slave mode LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB SDOn MSB OUT ...
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... NXP Semiconductors 10.4 XIN_OSC input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C mode, a minimum of 200 mV manual UM10316 ...
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... NXP Semiconductors 11. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors temperature MSL: Moisture Sensitivity Level Fig 40. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors 13. Abbreviations Table 46. Abbreviation AHB AMBA APB BCL BDL BEL BIST CCO CISC DMA DSP DTL EOP ETB ETM FIQ GPDMA IRQ LIN LSB MAC MSB MSC PHY PLL Q-SPI RISC SFSP SCL TTL UART 14. References [1] UM10316 — LPC29xx user manual [2] ARM — ...
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... NXP Semiconductors [4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — LIN specification package, revision 2.0 LPC2927_29_2 Preliminary data sheet ARM9 microcontroller with CAN, LIN, and USB Rev. 02 — 22 June 2009 www ...
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... NXP Semiconductors 15. Revision history Table 47. Revision history Document ID Release date LPC2927_29_2 20090622 • Modifications: Dynamic characteristics of CLKOUT pin added • Flash/EEPROM endurance and retention characteristics updated • Electrical pin characteristics added • External static memory timing parameters and diagrams updated Figure 5 • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2.1 General description 5.2.2 LQFP144 pin assignment . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 Architectural overview 6.2 ARM968E-S processor . . . . . . . . . . . . . . . . . . 12 6.3 On-chip flash memory system . . . . . . . . . . . . 13 6.4 On-chip static RAM 6.5 Memory map ...
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... NXP Semiconductors 6.15.6.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 47 6.15.7 Quadrature Encoder Interface (QEI 6.15.7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 48 6.15.7.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 48 6.16 Power, Clock and Reset Control Subsystem (PCRSS 6.16.1 Clock description . . . . . . . . . . . . . . . . . . . . . . 49 6.16.2 Clock Generation Unit (CGU0 6.16.2.1 Functional description 6.16.2.2 PLL functional description . . . . . . . . . . . . . . . 53 6.16.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 54 6.16.3 Clock generation for USB (CGU1 6.16.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 55 6.16.4 Reset Generation Unit (RGU ...