HY27SG162G2M Hynix Semiconductor, HY27SG162G2M Datasheet - Page 12

• Manufacturer Part Number: HY27SG162G2M
• Description: (HY27xx Series) 2G-Bit NAND Flash
• Manufacturer: Hynix Semiconductor

Preliminary
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an
Erase Setup command (60h). Only address A18 to A28 (X8) or A17 to A27 (X16) is valid while A12 to A17 (X8) or A11
to A16 (X16) is ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal
erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are
not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The sys-
tem controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of the
Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the
erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system per-
formance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copying-program with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back
command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is
required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant por-
tions of the source page is allowed as shown in Figure 15.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 17 shows the command sequence for the copy-back operation.
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or
RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when RB# pins are common-wired. RE# or CE# does not need to be toggled for updated
status. Refer to table 15 for specific Status Register definitions. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read
command (00h) should be given before starting read cycles. See figure 11 for details of the Read Status operation.
Rev 0.2 / Mar. 2005
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