HY27SG162G2M Hynix Semiconductor, HY27SG162G2M Datasheet - Page 13

• Manufacturer Part Number: HY27SG162G2M
• Description: (HY27xx Series) 2G-Bit NAND Flash
• Manufacturer: Hynix Semiconductor

3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h,
4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 20 shows the operation sequence, while tables 16 to 17 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high. If the device
is already in reset state a new reset command will not be accepted by the command register. The RB# pin transitions
to low for tRST after the Reset command is written. Refer to figure 25.
3.8 Cache Program.
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data
input may be executed while data stored in data register are programmed into memory cell. After writing the first set
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-
mand (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period
of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers
become ready by polling the Cache-Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon
the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by
the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The
status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the progress of programming only with RB#, the last page of the target programming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See figure 18 for more details.
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page -
Rev 0.2 / Mar. 2005
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the
last page is initiated only after completion of the previous cycle, which can be expressed as the following
formula.
(Program command cycle time + Last page data loading time)
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
Preliminary
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