MT24D836 Micron Technology, Inc, MT24D836 Datasheet - Page 8

• Manufacturer Part Number: MT24D836
• Description: DRAM Module
• Manufacturer: Micron Technology, Inc

OBSOLETE
NOTES
1. All voltages referenced to V
2. This parameter is sampled. Capacitance is measured
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
6. An initial pause of 100 s is required after power-up,
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate specifica-
10. If CAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL gates
13. If CAS# is LOW at the falling edge of RAS#, Q will be
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
V
Specified values are obtained with minimum cycle
time and the outputs open.
cycle time at which proper operation over the full
temperature range is ensured.
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
requirement is exceeded.
measuring timing of input signals. Transition times
are measured between V
and V
tion, all input signals must transit between V
V
last valid READ cycle.
and 100pF, V
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
CC
CC
IH
IL
is dependent on output loading and cycle rates.
(or between V
(MIN) and V
= 4.5V, DC bias = 2.4V at 15mV RMS).
IH
).
IH
IL
OL
, data output may contain data from the
, data output is High-Z.
= 0.8V and V
IL
t
IL
CP.
(MAX) are reference levels for
and V
IH
IH
t
and V
T = 5ns.
) in a monotonic manner.
SS
OH
.
= 2V.
t
IL
REF refresh
(or between V
IH
and
IL
8
14. The
15. The
16. Either
17.
18. These parameters are referenced to CAS# leading
19. OE# is tied permanently LOW; LATE WRITE or
20. A HIDDEN REFRESH may also be performed after
21. The 3ns minimum is a parameter guaranteed by
22. Column address changed once each cycle.
23. 16MB module values will be half of those shown.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
t
without the
always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
t
without the
must always be met.
cycle.
t
achieves the open circuit condition and is not
referenced to V
edge in EARLY WRITE cycles.
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted.
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
design.
RCD was greater than the specified
CAC (
RAD was greater than the specified
AA (
OFF (MAX) defines the time at which the output
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
t
RAC and
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RCH or
RAC [MIN] no longer applied). With or
t
t
RCD (MAX) limit,
RAD (MAX) limit,
OH
t
t
RRH must be satisfied for a READ
CAC no longer applied). With or
or V
PARITY DRAM SIMMs
OL
.
t
t
AA and
AA,
4, 8 MEG x 36
t
t
t
RCD (MAX)
RAD (MAX)
RAC and
„1997, Micron Technology, Inc.
t
CAC must
t
t
RCD
RAD
t
CAC