MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 32

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Power Up Sequence
On power up, the RESET pin must be held low for 100µs. Forcing the RESET pin low will put the MT93L00 in
power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated.
The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500µs for PLL to lock.
C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups of
echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control
Register.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00H to Base Address+3FH, to
the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00H
to Base Address+3FH, for the specific application.
Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
Group 0
Echo
Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Groups 2 --> 14
Echo Cancellers
Registers
Group 15
Echo
Cancellers
Registers
Figure 8 - Memory Mapping
Channel 0, EC A Ctrl/Stat Registers
Channel 1, EC B Ctrl/Stat Registers
Channel 2, EC A Ctrl/Stat Registers
Channel 3, EC B Ctrl/Stat Registers
Channel 30, EC A Ctrl/Stat Registers
Channel 31, EC B Ctrl/Stat Registers
Main Control Registers <15:0>
Interrupt FIFO Register
Test Register
Zarlink Semiconductor Inc.
MT93L04
32
0000h -->
0020h -->
0040h -->
0060h -->
03C0h -->
03E0h -->
0400h --> 040Fh
0410h
0411h
001Fh
003Fh
005Fh
007Fh
03DFh
03FFh
Data Sheet