MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 8

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
MCLK_d1
Fsel_d1
Step_d1
PLLVSS1_d1
PLLVDD_d1
PLLVSS2_d1
AT1_d1
DEVICE 2
TMS_d2
TDI_d2
TDO_d2
TCK_d2
TRSTB_d2
Sg1_d1
DT1_d1
Halt_d1
Signal Name
ICO
NC
User Signal
User Signal
ICO
ICO
Power
Power
Power
NC
Signal
Signal
Signal
Signal
Signal
Signal Type
BGA Ball #
W3
W4
E4
D1
E1
G3
G2
G1
V4
Y2
Y3
Zarlink Semiconductor Inc.
F3
E2
F2
F1
MT93L04
8
Internal Connection. Connected to VSS for
normal operation
No connection. The pin must be left open for
normal operation.
Master Clock (Input). Nominal 10 MHz or
20 MHz Master Clock input. May be connected to
an asynchronous (relative to frame signal) clock
source.
Frequency select (Input). This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2 MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6 MHz Master Clock input must be applied.
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
PLL Ground. Must be connected to VSS
PLL Power Supply. Must be connected to VDD2
PLL Ground. Must be connected to VSS
No connection. The pin must be left open for
normal operation.
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data In (3.3 V Input). JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data Out (Output). JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
Test Clock (3.3 V Input). Provides the clock to
the JTAG test logic.
Test Reset (3.3 V Input). Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Signal Description
Data Sheet