MT8910 Zarlink Semiconductor, MT8910 Datasheet - Page 20

• Manufacturer Part Number: MT8910
• Description: Digital Subscriber Line Interface Circuit
• Manufacturer: Zarlink Semiconductor

MRST, OSC1, C4b, F0b and SFb. TSTout=0 if all
input signals carry an even number of ones and
TSTout=1 if all input signals carry an odd number of
ones.
The I/O structure test also allows the verification of
the connection between the digital output pins and
the printed circuit board.
initialization sequence, the I/O structure output test
can be enabled by setting the TSTen to a logic high
with the mode select pins MS0, MS1 and NT/LT set
to 1, 1, 0 respectively. This causes all digital outputs
to be driven from the I/O structure test input (TSTin)
pin1.
CDSTo, F0od and TSTout
These same outputs can also be placed into a high
impedance state to allow the bed-of-nails tester or
some other in-circuit tester to drive a known signal or
pattern on any circuitry that may be connected to the
output pins of the MT8910-1. The high impedance
state is enabled by running the initialization pattern
described above then setting TSTen to a logic one
with the mode select pins MS0, MS1 and NT/LT set
to 1, 0, 0 respectively.
Note
1
:
74HC04
The outputs affected include the DSTo,
Allow a propagation delay of approximately 800ns
from digital input to XOR output or TSTin to any
digital output.
12ms Superframe Pulse
10.24 MHz Clock
8 kHz Frame Pulse
4.096 MHz Clock
System Reset
PCM or Data Out
PCM or Data In
74HC04
Figure 11 - Typical Connections for LT Mode (Single Port)
*
After running the
20
19
17
18
16
12
13
14
15
21
6
8
4
5
7
3
OSC1
OSC2
C4b
F0b
SFb
DSTi
DSTo
MS0
MS1
NT/LT
TSTin
TSTen
CDSTi
MRST
VSS
AVSS
MT8910-1
CDSTo
TSTout
AVDD
VBias
Lout+
Lout-
F0od
VRef
VDD
Lin+
Lin-
IC
22
24
28
27
25
26
23
11
10
2
1
9
1 F
1 F
Applications
The typical connection diagrams are shown in
Figures 11 and 12.
receives all its timing from the system including the
C4b, F0b and a frequency-locked 10.24 MHz master
clock. In Figure 12, the MT8910-1 is configured in
the NT mode which implies that all timing signals
including the F0b, C4b and SFb are being sourced
from the MT8910-1.
generated from an internal DPLL which divides a
10.24 MHz reference frequency down to a baseband
160 kHz.
reference signal with the received line signal to
determine if the timing signals on the MT8910-1
have to be corrected.
The MT8910-1 is interfaced to the transmission line
through the Passive Line Termination network (PLT)
and transformer. The PLT provides the two to four
wire
compensation for the received signal.
circuit is DC isolated from the line by the low
inductance transformer.
1.0 F
PLT
conversion
M
H
8
9
1
0
1
0.1 F
0.1 F
V
DD
TO NEXT DSLIC
A comparison
IN CHAIN
1.0 F
1:1.3
1.5 F
and
In Figure 11, the MT8910-1
TO LINE FEED
SUPPLY
These timing signal are
*Duty cycle: 45% to 55%
additional
is performed on the
MT8910-1
The whole
frequency
9-21