MT8910 Zarlink Semiconductor, MT8910 Datasheet - Page 3

• Manufacturer Part Number: MT8910
• Description: Digital Subscriber Line Interface Circuit
• Manufacturer: Zarlink Semiconductor

MT8910-1
9-4
Pin Description
PDIP PLCC
10
11
12
13
1
2
3
4
5
6
7
8
9
Pin #
CDSTo
TSTout
CDSTi
NT/LT
AVSS
TSTin
DSTo
Lout+
Lout-
F0od
12
13
14
15
16
18
19
20
DSTi
VSS
MS0
MS1
1
3
5
6
8
CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and
TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an
CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and
Name
TSTin
AV
DSTo
10
11
12
13
14
F0od
L
DSTi
MS0
MS1
1
2
3
4
5
6
7
8
9
L
V
out+
28 PIN PDIP
out-
SS
SS
Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
Analog Ground. Tie to V
I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
for normal operation.
C-channels in Dual mode. Unused in Single mode and should be connected to V
Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
Ground.
Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
Mode Select 0. CMOS input. Refer to Table 1.
Mode Select 1. CMOS input. Refer to Table 1.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Lin+
Lin-
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
C4b
SFb
TSTen
Bias
.
Bias
Figure 2 - Pin Connections
.
SS
.
CDSTo
CDSTi
DSTo
DSTi
F0od
VSS
Description
NC
NC
NC
NC
NC
18 19 20 21 22
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2
44 PIN PLCC
23
1
24 25 26 27 28
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
NC
AVDD
NC
NC
NC
IC
VDD
MRST
OSC1
OSC2
NC
SS
.
SS