MT8910 Zarlink Semiconductor, MT8910 Datasheet - Page 4

• Manufacturer Part Number: MT8910
• Description: Digital Subscriber Line Interface Circuit
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
PDIP PLCC
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin #
9 -11,
2,4,7,
17,24
26,28
29,35
36,37
39,40
21
22
23
25
27
30
31
32
33
34
38
41
42
43
44
TSTen I/O Structure Test Enable Input. This active high input enables the built-in test of all
MRST Master Reset. Active low CMOS input performs a master reset of the DSLIC.
Name
NT/LT
OSC2
OSC1
AV
V
V
SFb
C4b
V
F0b
L
L
NC
IC
Bias
Ref
DD
in+
in-
DD
NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When
low, LT mode is selected.
digital input and output structures. Refer to “I/O Structure Test" in functional description for
more details. Tie to V
Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which,
when low during a falling edge of C4b within an F0b low pulse, sets the transmit
superframe boundary.
In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the
transmit superframe. In NT mode, the superframe timing is generated from the line signal
time base and, as such, SFb will only be valid once the transceiver has achieved full
activation.
4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096
kHz ST-BUS clock output frequency locked to the line signal.
Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS
channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating
the start of the active ST-BUS channel times.
Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT
mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz 5ppm
clock (see “10.24 MHz Clock Interface" section).
When operating with a crystal (typically NT mode) connect one lead of the fundamental
mode parallel resonator crystal (10.24 MHz 50ppm in case of NT mode).
Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode)
connect OSC1 to the input of an external inverter (see Fig.11).
When operating with a crystal (typically NT mode) connect the other lead of the
fundamental mode parallel resonator crystal (10.24 MHz 50ppm in case of NT mode).
Power Supply Input.
Internal Connection. Leave unconnected.
Analog Power Supply. Connect to V
Bias Voltage. Decouple to AV
Reference Voltage. Decouple to AV
Line Signal Input Minus. Internally biased at V
Line Signal Input Plus. Internally biased at V
No Connection. Leave circuit open.
SS
for normal operation.
SS
through a 1.0 F ceramic capacitor.
SS
DD
Description
through a 1.0 F ceramic capacitor.
.
Bias.
Bias.
MT8910-1
9-5