ADC0808S250 NXP Semiconductors, ADC0808S250 Datasheet - Page 7

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ADC0808S250

Manufacturer Part Number
ADC0808S250
Description
(ADC0808S125 / ADC0808S250) Single 8-bit ADC
Manufacturer
NXP Semiconductors
Datasheet

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ADC0808S125_ADC0808S250_3
Product data sheet
7.3 Timing output
7.4 Timing complete conversion signal
The ADC0808S generates an adjustable clock output signal on pin CCS called Complete
Conversion Signal, which can be used to control the acquisition of converted output data
to the digital circuit connected to the ADC0808S output data bus.
Two logic input pins DEL0 and DEL1 control the delay of the edge of the CCS signal to
achieve an optimal position in the stable, usable zone of the data as shown in
Table 7.
Pin CCSSEL selects the CCS frequency; see
Table 8.
Pin DEL0
LOW
HIGH
LOW
HIGH
Pin CCSSEL
HIGH or not connected
LOW
Fig 5.
Output timing diagram (CCS not selected)
Complete conversion signal selection
Complete conversion signal frequency selection
CLK+, CLK
D0 to D7
Pin DEL1
LOW
LOW
HIGH
HIGH
IN, INN
Rev. 03 — 24 February 2009
sample
n
n
t
d(s)
Pin CCS
high-impedance
active; see
n
data
2
sample
n
1
Table 13
Single 8-bit ADC, up to 125 MHz or 250 MHz
n
data
CCS frequency (f
f
f
clk
clk
Table
1
sample
/ 2
n
ADC0808S125/250
t
d(o)
2
8.
t
h(o)
data
n
sample
n
CCS
3
)
n
data
001aab892
1
© NXP B.V. 2009. All rights reserved.
sample
n
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Figure
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6.

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