HD3-15530-9 Intersil Corporation, HD3-15530-9 Datasheet - Page 3

• Manufacturer Part Number: HD3-15530-9
• Description: CMOS Manchester Encoder-decoder
• Manufacturer: Intersil Corporation

Pin Description
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word
the SEND DATA output will go high and remain high for six-
teen ENCODER SHIFT CLOCK periods
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
I = Input
NUMBER
PIN
18
19
20
21
22
23
24
SYNC SELECT
SEND DATA
SHIFT CLK
SEND CLK
ZERO OUT
ENCODER
ENCODER
BIPOLAR
ONE OUT
BIPOLAR
ENABLE
DATA IN
SERIAL
TIMING
O = Output
2
TYPE
. When the Encoder is ready to accept data,
O
I
I
I
I
I
I
SERIAL DATA IN
ENCODER ENABLE
SYNC SELECT
SEND DATA
SEND CLOCK IN
ENCODER CLOCK
V
(Continued)
CC
1 2
VALID
NAME
1ST HALF
SYNC
0
1
2ND HALF
SYNC
3
3
2
SECTION
. During these
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
15
Both
DON’T CARE
15
15
3
DON’T CARE
14
14
14
4
HD-15530
Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
Actuates a Command sync for an input high and Data sync for an input low.
An active high output which enables the external source of serial data.
Clock input at a frequency equal to the data rate X2, usually driven by
output.
Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
V
(pin 24) to GROUND (pin 12) is recommended.
FIGURE 1.
13
1
CC
5-144
.
13
13
5
is the +5V power supply pin. A 0.1 F decoupling capacitor from V
12
ENCODER SHIFT CLOCK so it can be sampled on the low-
to-high transition
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
must go low by time
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
12
12
6
11
11
11
7
10
3
15
3
3
3
DESCRIPTION
-
2
5
16
4
2
2
as shown to prevent a consecutive
. After the sync and Manchester II
1
17
1
1
0
18
0
0
4 5
19
P
P
5
. If ENCODER
CC
6