HD3-15530-9 Intersil Corporation, HD3-15530-9 Datasheet - Page 4

• Manufacturer Part Number: HD3-15530-9
• Description: CMOS Manchester Encoder-decoder
• Manufacturer: Intersil Corporation

Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can only
accept non-inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
COMMAND/DATA SYNC output. If the sync character was a
command sync, this output will go high
for sixteen DECODER SHIFT CLOCK periods
it will remain low. The TAKE DATA output will go high and
remain high
decoded data through SERIAL DATA OUT. The decoded
VALID WORD
COMMAND/
DATA SYNC
TAKE DATA
SHIFT CLK
DECODER
DATA OUT
BIPOLAR
BIPOLAR
ZERO IN
SERIAL
TIMING
ONE IN
2
-
3
(FROM PREVIOUS RECEPTION)
1
while the Decoder is transmitting the
, the type of sync is indicated on
1ST HALF
SYNC
0
UNDEFINED
1
2ND HALF
SYNC
2
2
15
15
3
and remain high
14
14
4
3
, otherwise
1
2
13
13
5
15
HD-15530
FIGURE 2.
12
12
6
5-145
14
data available at SERIAL DATA OUT is in NRZ format. The
DECODER SHIFT CLOCK is provided so that the decoded
bits can be shifted into an external register on every low-to-
high transition of this clock
SHIFT CLOCK may adjust its phase up until the time that
TAKE DATA goes high.
After all sixteen decoded bits have been transmitted
data is checked for odd parity. A high on VALID WORD
output
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
11
11
7
13
10
10
8
12
4
indicates a successful reception of a word without
1
16
2
2
.
4
17
1
1
3
18
0
0
2
2
19
-
P
P
1
3
. Note that DECODER
0
3
4
3
the