AD1896 Analog Devices, AD1896 Datasheet

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... MCLK internally to reduce noise and EMI emissions on the board. When MCLK is synchronous to either the output or input serial port, the AD1896 can be configured in a master mode where MCLK is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to MCLK. ...

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... AD1896–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages VDD_CORE 3.3 V VDD_IO 5 3.3 V Ambient Temperature 25°C Input Clock 30.0 MHz Input Signal 1.000 kHz, 0 dBFS Measurement Bandwidth S_OUT Word Width 24 Bits Load Capacitance 50 pF Input Voltage HI 2.4 V Input Voltage LO 0.8 V Specifications subject to change without notice. ...

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... MCLK < 70°C, 45/55 or better MCLK_I duty cycle. A MCLK I t SIH t SIL t SOH t SOL t DOH 10%) Min Max 33 30 200 RESET t RSTL RESET t MPWH t MPWL AD1896 Unit ns MHz ...

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... AD1896–SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage Input Voltage Input Leakage ( Input Leakage (I ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1896 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... Master/Slave Clock Ratio Mode Select Pin 0 Master/Slave Clock Ratio Mode Select Pin 1 Master/Slave Clock Ratio Mode Select Pin 2 PIN CONFIGURATION GRPDLYS 1 MMODE_2 28 MCLK_IN 2 27 MMODE_1 MCLK_OUT 3 26 MMODE_0 AD1896 SDATA_I 4 25 SCLK_O TOP VIEW SCLK_I 5 24 LRCLK_O ) (NOT TO SCALE LRCLK_I 6 SDATA_O 23 ...

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... FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz Typical Performance Characteristics–AD1896 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 10 20.0 22.5 0 –20 –40 –60 –80 –100 –120 –140 – ...

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... AD1896 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz –50 –60 –70 –80 –90 –100 –110 –120 – ...

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... FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 20.0 22.5 2.5 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 20.0 22.5 2.5 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 20.0 22.5 2.5 AD1896 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY – kHz 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY – kHz ...

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... AD1896 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz – ...

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... AD1896 80 105 130 155 180 OUTPUT SAMPLE RATE – kHz 80 105 130 155 180 OUTPUT SAMPLE RATE – kHz 80 105 130 155 180 OUTPUT SAMPLE RATE – kHz ...

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... AD1896 –130 –131 –132 –133 –134 –135 –136 –137 –138 –139 –140 105 130 OUTPUT SAMPLE RATE – kHz 0 –20 –40 192kHz:96kHz –60 192kHz:48kHz –80 –100 192kHz:32kHz –120 –140 FREQUENCY – kHz –135 –136 –137 –138 –139 –140 – ...

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... AD1896 – – – – – 0 100 INPUT LEVEL – dBFS – – – – – 0 100 INPUT LEVEL – dBFS – ...

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... AD1896 –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 –140 –120 –100 –80 –60 INPUT LEVEL – dBFS –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 –140 – ...

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... The AD1896 input tolerant part and is available in a 28-lead SSOP SMD package. The AD1896 input- tolerant only when the VDD_IO supply pin is supplied with 5 V. ...

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... Since the ratio irra- tional number, the error resulting from the resampling at f can never be eliminated. However, the error can be signifi- cantly reduced through interpolation of the input data at f The AD1896 is conceptually interpolated by a factor ZERO-ORDER HOLD ...

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... Since there are 2 with a 64-tap FIR filter, there needs cients for each tap, which requires a total of 2 reduce the amount of coefficients in ROM, the AD1896 stores a small subset of coefficients and performs a high-order interpola- tion between the stored coefficients. So far the above approach works for the case of f > ...

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... AD1896 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution ...

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... I/O pins. While RESET is active low, the AD1896 is consuming minimum power. For the lowest possible power consumption while RESET is active low, all of the input pins to the AD1896 should be static. When RESET is deasserted, the AD1896 begins its initialization ...

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... C2 There are, of course, maximum and minimum operating fre- quencies for the AD1896 master clock. The maximum master clock frequency at which the AD1896 is guaranteed to operate is 30 MHz. 30 MHz is more than sufficient to sample rate convert sampling frequencies of 192 kHz + 12%. The minimum required frequency for the master clock generation for the AD1896 depends upon the input and output sample rates ...

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... MSB TDM MODE – BITS PER CHANNEL 1/f s LRCLK EXCEPT FOR TDM MODE WHICH the next AD1896, a large shift register is created which is clocked by SCLK_O. ® DSP. The The number of AD1896s that can be daisy-chained together is limited by the maximum frequency of SCLK_O, which is about 25 MHz. For example, if the output sample rate eight AD1896s could be connected since 512 × ...

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... Serial Data Port Master Clock Modes Either of the AD1896 serial ports can be configured as a master serial data port. However, only one serial port can be a master while the other has slave. In master mode, the AD1896 requires a 256 × 768 × 512 f master clock (MCLK_I) ...

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... AUDIO DATA LEFT CHANNEL, 24 BITS MATCHED-PHASE AUDIO DATA LEFT CHANNEL, DATA, 8 BITS configured as the master while the rest of the AD1896s in the chain would be configured as slaves with their MMODE_2, MMODE_1, and MMODE_0 pins set to 100 respectively. Please note that in the left-justified, I lower eight bits of each channel subframe are used to transmit the matched-phase data ...

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... AD1896 PIN 1 0.079 (2.00) MAX 0.002 (0.05) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.413 (10.50) 0.402 (10.20) 0.390 (9.90 0.220 (5.60) 0.209 (5.30) 0.197 (5.00) 0.323 (8.20) 0.307 (7.80 0.291 (7.40) 0.073 (1.85) 0.069 (1.75) 0.065 (1.65) 0.026 0.015 (0.38) SEATING 0.010 (0.25) (0.65) 0.009 (0.22) PLANE MIN BSC 0.004 (0.09) –24– ...