AD1896 Analog Devices, AD1896 Datasheet - Page 6

• Manufacturer Part Number: AD1896
• Description: 192 kHz Stereo Asynchronous Sample Rate Converter
• Manufacturer: Analog Devices

AD1896
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Also used to input matched-phase mode data.
IN/OUT
IN
IN
OUT
IN
IN/OUT
IN/OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
IN/OUT
IN/OUT
IN
IN
IN
Mnemonic
GRPDLYS
MCLK_IN
MCLK_OUT
SDATA_I
SCLK_I
LRCLK_I
VDD_IO
DGND
BYPASS
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
RESET
MUTE_IN
MUTE_OUT
WLNGTH_OUT_1
WLNGTH_OUT_0
SMODE_OUT_1
SMODE_OUT_0
TDM_IN
DGND
VDD_CORE
SDATA_O
LRCLK_O
SCLK_O
MMODE_0
MMODE_1
MMODE_2
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
MCLK_OUT
GRPDLYS
MCLK_IN
PIN FUNCTION DESCRIPTIONS
MUTE_IN
SDATA_I
LRCLK_I
BYPASS
VDD_IO
SCLK_I
RESET
DGND
PIN CONFIGURATION
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(NOT TO SCALE
Group Delay HI = Short, LO = Long
Master Clock or Crystal Input
Master Clock Output or Crystal Output
Input Serial Data (at Input Sample Rate)
Master/Slave Input Serial Bit Clock
Master/Slave Input Left/Right Clock
3.3 V/5 V Input/Output Digital Supply Pin
ASRC Bypass Mode, Active High
Input Port Serial Interface Mode Select Pin 0
Input Port Serial Interface Mode Select Pin 1
Input Port Serial Interface Mode Select Pin 2
Mute Input Pin— Active HI Normally Connected to MUTE_OUT
Output Mute Control – Active HI
Hardware Selectable Output Wordlength—Select Pin 1
Hardware Selectable Output Wordlength—Select Pin 0
Output Port Serial Interface Mode Select Pin 1
Output Port Serial Interface Mode Select Pin 0
Serial Data Input (only for Daisy Chain Mode). Ground when not used.
3.3 V Digital Supply Pin
Output Serial Data (at Output Sample Rate)
Master/Slave Output Left/Right Clock
Master/Slave Output Serial Bit Clock
Master/Slave Clock Ratio Mode Select Pin 0
Master/Slave Clock Ratio Mode Select Pin 1
Master/Slave Clock Ratio Mode Select Pin 2
Description
Digital Ground Pin
Reset Pin, Active Low
Digital Ground Pin
AD1896
TOP VIEW
)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MMODE_1
MMODE_0
SCLK_O
LRCLK_O
SDATA_O
VDD_CORE
DGND
TDM_IN
SMODE_OUT_0
SMODE_OUT_1
WLNGTH_OUT_0
WLNGTH_OUT_1
MUTE_OUT
MMODE_2