AD1896 Analog Devices, AD1896 Datasheet - Page 20

• Manufacturer Part Number: AD1896
• Description: 192 kHz Stereo Asynchronous Sample Rate Converter
• Manufacturer: Analog Devices

AD1896
There are, of course, maximum and minimum operating fre-
quencies for the AD1896 master clock. The maximum master
clock frequency at which the AD1896 is guaranteed to operate is
30 MHz. 30 MHz is more than sufficient to sample rate convert
sampling frequencies of 192 kHz + 12%. The minimum required
frequency for the master clock generation for the AD1896 depends
upon the input and output sample rates. The master clock has
to be at least 138 times greater than the maximum input or
output sample rate.
Serial Data Ports—Data Format
The serial data input port mode is set by the logic levels on the
SMODE_IN_0/1/2 pins. The serial data input port modes avail-
able are Left Justified, I
or 24 bits as defined in Table I.
AD1896
MCLK_I
AD1896
MCLK_I
C1
C1
2
S and Right Justified (RJ), 16, 18, 20,
MCLK_O
R = 45
C2
MCLK_O
R = 45
C2
1nF
L1
2
0
0
0
0
1
1
1
1
The serial data output port mode is set by the logic levels on the
SMODE_OUT_0/1 and WLNGTH_OUT_0/1 pins. The serial
mode can be changed to Left Justified, I
TDM as defined in the following table. The output word width
can be set by using the WLNGTH_OUT_0/1 pins as shown in
the Word Width table. When the output word width is less than
24 bits, dither is added to the truncated bits. The Right Justified
serial data out mode assumes 64 SCLK_O cycles per frame,
divided evenly for left and right. Please note that 8 bits of each
32-bit subframe are used for transmitting Matched Phase mode
data. Please refer to Figure 14.
SMODE_OUT_[0:2]
1
0
0
1
1
WLNGTH_OUT_[0:1]
1
0
0
1
1
The following timing diagrams show the serial mode formats.
SMODE_IN_[0:2]
1
0
0
1
1
0
0
1
1
Table II. Serial Data Output Port Mode
Table I. Serial Data Input Port Mode
0
0
1
0
1
0
0
1
0
1
Table III. Word Width
0
0
1
0
1
0
1
0
1
Interface Format
Left Justified (LJ)
I
TDM Mode
Right Justified (RJ)
Word Width
24 Bits
20 Bits
18 Bits
16 Bits
2
S
Interface Format
Left Justified
I
Undefined
Undefined
Right Justified, 16 Bits
Right Justified, 18 Bits
Right Justified, 20 Bits
Right Justified, 24 Bits
2
S
2
S, Right Justified or