74ALVCH16623DL,118 NXP Semiconductors, 74ALVCH16623DL,118 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16623DL,118
• Description: IC 16BIT TXRX 3-ST 48-SSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16623DL,118

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16623DL-T; 74ALVCH16623DL-T; 935254340118

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
Ground = 0; T
Notes
1. C
2. The condition is V
1999 Sep 20
t
C
C
C
PHL
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
standard pin-out architecture
All data inputs have bus hold
circuitry
Output drive capability 50
transmission lines at 85 C
Current drive 24 mA at 3.0 V.
I/O
I
PD
16-bit transceiver with dual enable; 3-state
SYMBOL
P
f
C
f
V
i
o
/t
D
CC
PD
= input frequency in MHz;
L
(C
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
V
2
propagation delay nA
input/output capacitance
input capacitance
power dissipation capacitance per buffer notes 1 and 2
CC
flow-through
= 25 C; t
f
2
o
) = sum of outputs.
I
f
= GND to V
i
+
r
= t
(C
PARAMETER
L
f
= 2.5 ns.
V
CC
CC
.
n
, nB
2
DESCRIPTION
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOE
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling of nOE
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OE
should be tied to V
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
f
n
o
) where:
to nB
n
, nA
n
C
C
CC
2
L
L
outputs enabled
outputs disabled
= 30 pF; V
= 50 pF; V
through a pull-up resistor and OE
D
in W).
CONDITIONS
AB
CC
CC
AB
and nOE
= 2.5 V
= 3.3 V
, nOE
BA
BA
). The enable inputs can be used to
. Each output reinforces its input in
2.0
1.9
10.0
3.0
35
5
TYPICAL
74ALVCH16623
AB
Product specification
should be tied to GND
ns
ns
pF
pF
pF
pF
UNIT
BA