MT28F008B5 Micron Technology, MT28F008B5 Datasheet - Page 12

• Manufacturer Part Number: MT28F008B5
• Description: (MT28F008B5 / MT28F800B5) FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
COMMAND EXECUTION
ferent operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the proper-
ties of each mode, and Table 3 lists all command
sequences required to perform the desired operation.
Read Array
upon power-up and after a RESET. If the device is in
any other mode, READ ARRAY (FFh) must be given to
return to the array read mode. Unlike the WRITE
SETUP command (40h), READ ARRAY does not need
to be given before each individual read access.
IDENTIFY DEVICE
to enter the identify device mode. While the device is
in this mode, any READ produces the device ID when
A0 is HIGH and the manufacturer compatibility ID
when A0 is LOW. The device remains in this mode until
another command is given.
Write Sequence
the array. WRITE SETUP (40h or 10h) is given in the
Table 3:
Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
4
U
Commands are issued to bring the device into dif-
The array read mode is the initial state of the device
IDENTIFY DEVICE (90h) may be written to the CEL
Two consecutive cycles are needed to input data to
.com
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. BA = Block Address (A12–A19).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
Command Sequences
CYCLES
REQ’D
BUS
1
3
2
1
2
2
2
2
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
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FIRST CYCLE
SMART 5 BOOT BLOCK FLASH MEMORY
ADDRESS
X
X
X
X
X
X
X
X
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and V
brought to V
requires that the RP# pin be brought to V
pin be brought HIGH at the same time V
to V
V
(SR7 = 1).
bit (SR7) is at “0,” and the device does not respond to
any commands. Any READ operation produces the
status register contents on DQ0–DQ7. When the ISM
status bit (SR7) is set to a logic 1, the WRITE has been
completed, and the device enters status register read
mode until another command is given.
aborted except by a RESET or by powering down the
part. Doing either during a WRITE corrupts the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
a null WRITE. To execute a null WRITE, FFh must be
written when BYTE# is LOW, or FFFFh must be written
when BYTE# is HIGH. When the ISM status bit (SR7)
has been set, the device is in the status register read
mode until another command is issued.
PP
While the ISM executes the WRITE, the ISM status
After the ISM has initiated the WRITE, it cannot be
12
PPH
must be held at V
DATA OPERATION
Micron Technology, Inc. Reserves the right to change products or specifications without notice.
90h
70h
50h
20h
B0h
40h
10h
FFh
. The ISM now begins to write the word or byte.
PPH
WRITE
WRITE
WRITE
WRITE
READ
READ
. Writing to the boot block also
SECOND CYCLE
PPH
until the write is completed
ADDRESS
WA
WA
BA
IA
X
X
©2002, Micron Technology Inc.
DATA
HH
SRD
D0h
D0h
WD
WD
PP
ID
or the WP#
is brought
8Mb
NOTES
2, 3
5, 6
6, 7
6, 7
PP
1
4
is