MT28F160A3 Micron Technology, MT28F160A3 Datasheet - Page 7

• Manufacturer Part Number: MT28F160A3
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
MEMORY ORGANIZATION
blocks of 32K words, along with eight 4K-word parameter
blocks. The device is available with block architecture
mapped in either of the two configurations: the boot
blocks located at the top or at the bottom of the memory
array, as required by different microprocessors. The
MT28F160A3 top boot configuration with the blocks and
address ranges is shown in Figure 1 and the bottom boot
configuration in Figure 2.
are seldom changed during normal operation. When the
WP# is at V
erased or reprogrammed. The boot block contents can be
changed only through proper command sequences when
WP# is HIGH (see Table 5).
COMMAND STATE MACHINE
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between the external
microprocessor and the internal write state machine
(WSM). The available commands are listed in Table 2,
and the descriptions of these commands are shown in
Table 3. Program and erase algorithms are automated by
an on-chip WSM. Once a valid program/erase command
sequence is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing signals
to control the device internally to accomplish the re-
quested operation. A command is valid only if the exact
sequence of WRITEs is completed. After the WSM com-
pletes its task, the WSM status bit (SR7) is set to a logic
HIGH level (1), allowing the CSM to respond to the full
command set again.
1 Meg x 16 Enhanced Boot Block Flash Memory
MT28F160A3_3.p65 – Rev. 3, Pub. 8/01
4
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The MT28F160A3 memory array is segmented into 31
The boot blocks are used to store key system data and
Commands are issued to the command state ma-
.com
IL
, the contents of the boot block cannot be
ENHANCED BOOT BLOCK FLASH MEMORY
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7
OPERATION
JEDEC 8-bit command codes with conventional micro-
processor timings into an on-chip CSM through I/Os
DQ0-DQ7. When the device is powered up, internal reset
circuitry initializes the chip to a read array mode of op-
eration. Changing the mode of operation requires that a
command code be entered into the CSM. The on-chip
status register allows the progress of various operations
to be monitored. The status register is interrogated by
entering a READ STATUS REGISTER command onto the
CSM (cycle 1) and reading the register data on I/Os DQ0-
DQ7 (cycle 2). Status register bits SR0-SR7 correspond to
DQ0-DQ7 (see Table 3).
60h, 0Fh, AFh
COMMAND
Command State Machine Codes for
DQ0-DQ7
Device operations are selected by entering standard
10h/40h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D0h
20h
50h
70h
90h
B0h
FFh
Device Mode Selection
CODE ON
DEVICE MODE
Write setup/alternate write setup
Block erase setup
Clear status register
Read status register
Identify device
Program/erase suspend
Program/erase resume
Erase confirm
Read array
Reserved
Table 2
1 MEG x 16
©2001, Micron Technology, Inc.
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