MT55L256V36F Micron Technology, MT55L256V36F Datasheet - Page 10

• Manufacturer Part Number: MT55L256V36F
• Description: (MT55LxxxLxxF) 8Mb SRAM
• Manufacturer: Micron Technology

FBGA PIN DESCRIPTIONS (continued)
10L, 10M, 11D, 10L, 10M, 11J,
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_C.p65 – Rev. 2/02
2H, 4D, 4E, 4F, 2H, 4D, 4E, 4F,
11E, 11F, 11G 11K, 11L, 11M
(a)
1L, 1M, 2D, 10F, 10G, 11D,
4K, 4L, 4M,
3K, 3L, 3M,
3N, 9C, 9D,
4G, 4H, 4J,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
8D, 8E, 8F,
9E, 9F, 9G,
(b)
2E, 2F, 2G
3F, 3G, 3J,
9J, 9K, 9L,
9M, 9N
10J, 10K,
x18
11C
8A
1J, 1K,
1N
1R
–
–
11E, 11F, 11G
(d)
(b)
(a)
4K, 4L, 4M,
3K, 3L, 3M,
3N, 9C, 9D,
1F, 1G, 2D,
1M, 2J, 2K,
4G, 4H, 4J,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
8D, 8E, 8F,
9E, 9F, 9G,
3F, 3G, 3J,
9J, 9K, 9L,
2E, 2F, 2G
(c)
x32/x36
9M, 9N
2L, 2M
1J, 1K, 1L,
10D, 10E,
10J, 10K,
11N
11C
1D, 1E,
8A
1N
1 C
1R
ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
SYMBOL
NF/DQPb
NF/DQPd
NF/DQPa
NF/DQPc
MODE
(LB0#)
V
DQb
DQa
DQd
DQc
V
DD
DD
Q
Output Byte “ b” is associated with DQbs. For the x32 and x36 versions,
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Input/ SRAM Data I/Os: For the x18 version, Byte “ a” is associated DQas;
TYPE
Input
NF /
I/O
(continued on next page)
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
Mode: This input selects the burst sequence. A LOW on this
input selects “ linear burst.” NC or HIGH on this input selects
“ interleaved burst.” Do not alter input state while device is
operating.
Byte “ a” is associated with DQas; Byte “ b” is associated with DQbs;
Byte “ c” is associated with DQcs; Byte “ d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
No Function/Parity Data I/Os: On the x32 version, these are No
Function (NF). On the x18 version, Byte “ a” parity is DQPa; Byte
“ b” parity is DQPb. On the x36 version, Byte “ a” parity is DQPa;
Byte “ b” parity is DQPb; Byte “ c” parity is DQPc; Byte “ d” parity is
DQPd.
Conditions for range.
Operating Conditions for range.
10
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.