MT9V403 Micron, MT9V403 Datasheet - Page 2

• Manufacturer Part Number: MT9V403
• Description: 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
• Manufacturer: Micron

Table 1:
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
NUMBERS SIGNAL NAME
PIN
37
33
30
31
29
26
25
24
38
18
17
19
13
16
Pin Description
ROW_STRT
LD_SHFT_N
RESMEM
EXPOSE
SYSCLK
LRST_N
PG_N
TX_N
VLNS
VLN1
VOFF
SCLK
V
VLP
REF
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Expose
System
System
System
Clock
Reset
Clock
Data
Row
Two-Wire
Interface
Interface
Sensor
Figure 1: Block Diagram
Block
Serial
Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent,
±5 percent duty cycle).
Global logic RESET function (asynchronous). Active low pulse with minimum
duration 200ns.
Slave mode input signal. Starts row processing sequence of the pixel row (i.e.,
pixel readout, ADC conversion, and writing of data to ADC registers). The rising
edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A
one-clock cycle wide active high pulse. The two-wire serial interface register
setting switches this pin between input and output.
Slave mode input signal. An active LOW signal that enables the column counter
and initiates the readout process. Causes the 10-bit output port to be updated
with data on the rising edge of the system clock. The two-wire serial interface
register setting switches this pin between input and output.
Trigger for snapshot mode. The two-wire serial interface register setting
switches this pin between input and output. No connection should be made in
slave mode.
Slave mode input signal. Active low pulse that resets all photodetectors,
starting a new integration cycle. No connection should be made in master
mode or snapshot mode.
Slave mode input signal. Active low pulse that controls transfer of charge from
photodetector to memory inside each pixel for the entire pixel array. No
connection should be made in master mode or snapshot mode.
Slave mode input signal. Active low pulse to reset all pixel memories. No
connection should be made in master mode or snapshot mode.
Serial port clock. Maximum frequency is 1 MHz.
Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be
individually disconnected from their internal biases via the two-wire serial
interface and driven by this input.
Bias setting voltage for pixel source following operating current.
Bias setting voltage for the column source follower operating current.
Dark offset cancellation. Polarity of offset is set via the two-wire serial
interface.
Op amp bias.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
Control
Logic
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Calibration Data
Readout Control
Gain Control
Decoder
Row
2
ADC and Output Registers
667H x 10 SRAM (x2)
calibration memory
Column ADCs and
Pixel Array
Column PGA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTIONS
Output (9:0)
©2004 Micron Technology. Inc.