MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 20

• Manufacturer Part Number: MT8VDDT6464HD
• Description: (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
• Manufacturer: Micron Semiconductor Products

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Notes
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
10. I
11. This parameter is sampled. V
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
and V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. Thus, from V
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for-335 and -265 with the outputs open.
properly initialized, and is averaged at the defined
cycle rate.
V
25°C, V
DD
DD
REF
TT
DD
Q = +2.5V ±0.2V, V
is not applied directly to the device. V
specifications are tested after the device is
is dependent on output loading and cycle
is expected to equal V
IH
OUT
(AC).
REF
(DC) = V
REF
Output
(V
by-pass capacitor.
OUT
may not exceed ±2 percent of the
)
DD
DD
DD
V
tests may use a V
TT
REF
Q/2, V
50
30pF
, and electrical AC and DC
Reference
Point
Ω
DD
= V
SS
DD
Q/2, V
.
SS
OUT
REF
Q/2 of the transmit-
REF
DD
, f = 100 MHz, T
.
(peak to peak) =
and must track
= +2.5V ±0.2V,
REF
REF
is allowed
(or to the
IL
IL
-to-V
TT
(ACV)
is a
A
IH
=
20
12. Command/Address input slew rate = 0.5V/ns. For -
13. The CK/CK# input reference level (for timing ref-
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at the
16.
17. If DQS transitions to HIGH above V
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
21. The refresh period 64ms. This equates to an aver-
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
335, -262, -26A, and -265 with slew rates 1V/ns and
faster,
rate is less than 0.5V/ ns, timing must be derated:
t
reduction in slew rate from the 500mV/ns, while
t
4.5V/ns, functionality is uncertain.
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
lizes. Exception: during the period before V
stabilizes, CKE £ 0.3 x V
timing reference point indicated in Note 3, is V
t
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
then it must not transition to LOW below V
MIN prior to
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
ple of
value for
age refresh rate of 15.625µs (128MB) or 7.8125µs
(256MB, 512MB). However, an AUTO REFRESH
command must be asserted at least once every
140.6µs (128MB modules) or 70.3µs (256MB and
512MB modules); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
IS has an additional 50ps per each 100mV/ns
IH remains constant. If the slew rate exceeds
HZ and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MB, 256MB, 512MB (x64)
t
t
RC or
IS and
t
CK that meets the maximum absolute
t
t
LZ transitions occur in the same access
RAS.
DD
200-PIN DDR SODIMM
t
DQSH (MIN).
t
t
t
RFC) for I
measurements is the largest multi-
IH are reduced to 900ps. If the slew
DQSS.
t
CK that meets the minimum
REF
DD
©2003 Micron Technology, Inc. All rights reserved.
DD
Q is recognized as LOW.
.
measurements is the
IH
(DC) MIN,
REF
IH
TT
stabi-
(DC)
t
.
RAS
REF