HEF4024BP,652 NXP Semiconductors, HEF4024BP,652 Datasheet
HEF4024BP,652
Specifications of HEF4024BP,652
HEF4024BPN
HEF4024BPN
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HEF4024BP,652 Summary of contents
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HEF4024B 7-stage binary counter Rev. 05 — 9 November 2009 1. General description The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 ...
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... NXP Semiconductors 5. Functional diagram 7-STAGE COUNTER 001aab908 Fig 1. Functional diagram Fig 3. Logic diagram HEF4024B_5 Product data sheet Fig Rev. 05 — 9 November 2009 HEF4024B 7-stage binary counter 001aab906 Logic symbol 001aab909 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin n. 12, 11 Functional description [1] Table 3. Functional table Input HIGH voltage level LOW voltage level don’t care; HEF4024B_5 Product data sheet ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current DD T storage temperature stg ...
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... NXP Semiconductors Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I HIGH-level output current OH I LOW-level output current OL I input leakage current I I supply current DD C input capacitance I 11. Dynamic characteristics Table 7. Dynamic characteristics ...
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... NXP Semiconductors Table 7. Dynamic characteristics for test circuit see SS amb Symbol Parameter Conditions t transition time see t t pulse width CP HIGH; W minimum width see MR HIGH; minimum width see t recovery time MR; rec see f maximum CP input; max frequency HIGH; see [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C ...
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... NXP Semiconductors 12. Waveforms MR input CP input output V and V are typical output voltages levels that occur with the output load Measurement points are given in Fig 5. Waveforms showing propagation delays for and CP to Q0, minimum MR and CP pulse widths and recovery time for MR. Table 9. Measurement points ...
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... NXP Semiconductors a. Input waveforms b. Test circuit Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 6. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4024B_5 20091109 • Modifications: Section 9 “Recommended operating conditions” HEF4024B_4 20090902 HEF4024B_CNV_3 19950101 HEF4024B_CNV_2 19950101 HEF4024B_5 Product data sheet Data sheet status Change notice Product data sheet - Product data sheet - Product specifi ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Revision history ...