HEF4017BT,653 NXP Semiconductors, HEF4017BT,653 Datasheet

IC COUNTER 5STAGE JOHNSON 16SOIC

HEF4017BT,653

Manufacturer Part Number
HEF4017BT,653
Description
IC COUNTER 5STAGE JOHNSON 16SOIC
Manufacturer
NXP Semiconductors
Series
4000Br
Type
Decader
Datasheets

Specifications of HEF4017BT,653

Package / Case
16-SOIC (3.9mm Width)
Logic Type
Counter, Decade
Direction
Up
Number Of Elements
1
Number Of Bits Per Element
10
Reset
Asynchronous
Count Rate
30MHz
Trigger Type
Positive, Negative
Voltage - Supply
4.5 V ~ 15.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Counter Type
Decade Counters
Logic Family
HEF4017B
Number Of Bits
10
Operating Supply Voltage
3 V to 15 V
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Technology
CMOS
Number Of Elements
1
Logical Function
Counter/Divider
Operating Supply Voltage (typ)
3.3/5/9/12V
Output Type
Standard
Package Type
SO
Propagation Delay Time
290ns
Operating Temp Range
-40C to 125C
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
933372700653
HEF4017BTD-T
HEF4017BTD-T
1. General description
2. Features
3. Applications
The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active
HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop
(Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding
asynchronous master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR
resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock
inputs (CP0, CP1).
Automatic counter code correction is provided by an internal circuit: following any illegal
code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over both the industrial ( 40 C to +85 C) and automotive ( 40 C to
+125 C) temperature ranges.
I
I
I
I
I
I
I
I
HEF4017B
5-stage Johnson decade counter
Rev. 06 — 5 November 2009
Automatic counter correction
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Industrial and automotive
DD
power supply range of 3 V to 15 V referenced to V
DD
Table
, V
SS
, or another input. It is
3).
Product data sheet
SS

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HEF4017BT,653 Summary of contents

Page 1

HEF4017B 5-stage Johnson decade counter Rev. 06 — 5 November 2009 1. General description The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information All types operate from +125 C Type number Package Name Description HEF4017BP DIP16 plastic dual in-line package; 16 leads (300 mil) HEF4017BT SO16 plastic small outline package; 16 leads; body width 3 Functional diagram CP1 13 CP0 Fig 1. Functional diagram ...

Page 3

... NXP Semiconductors CP1 13 CP0 Fig 3. Logic symbol 6. Pinning information 6.1 Pinning Fig 5. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 10 Q5-9 12 CP1 13 HEF4017B_6 Product data sheet Q5-9 12 001aah239 Fig 4. HEF4017B CP0 CP1 Q5 001aae574 Description decoded output ground supply voltage ...

Page 4

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin CP0 Functional description [1] Table 3. Function table MR CP0 [ HIGH voltage level LOW voltage level don’t care; = positive-going transition; = negative-going transition. HEF4017B_6 Product data sheet Description clock input (LOW-to-HIGH edge-triggered) master reset input supply voltage ...

Page 5

... NXP Semiconductors CP0 INPUT CP1 INPUT MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q5-9 OUTPUT Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current ...

Page 6

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter I supply current DD T storage temperature stg T ambient temperature amb P total power dissipation tot P power dissipation [1] For DIP16 package: P derates linearly with 12 mW/K above 70 C. ...

Page 7

... NXP Semiconductors Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions I HIGH-level output current LOW-level output current input leakage I current I supply current input I capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics for test circuit see amb SS Symbol Parameter ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics for test circuit see amb SS Symbol Parameter Conditions t LOW to HIGH CP0, CP1 PLH propagation delay see CP0, CP1 see MR see MR see t transition time see t t hold time CP0 h see CP1 see t pulse width CP0 input LOW; ...

Page 9

... NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms CP0 input CP1 input output Q0 output Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition; The shaded areas indicate where the output state is set by the input count. ...

Page 10

... NXP Semiconductors CP0 input CP1 input MR input output Q0 output Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, t CP1 triggers on a HIGH-to-LOW transition. The shaded areas indicate where the output state is set by the input count. Measurement points given in Fig 8. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input ...

Page 11

... NXP Semiconductors a. Input waveforms b. Test circuit Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 10. Test circuit for measuring switching times Table 10. ...

Page 12

... NXP Semiconductors CP0 HEF4017B CP1 decoded outputs clock first stage Enabling the counter on CP1 when CP0 is HIGH CP0 when CP1 is LOW, causes an extra count. Fig 11. Counter expansion HEF4017B_6 Product data sheet MR MR CP0 HEF4017B CP1 - - - - - - - - decoded outputs intermediate stages Rev. 06 — 5 November 2009 ...

Page 13

... NXP Semiconductors 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 15

... NXP Semiconductors 15. Revision history Table 11. Revision history Document ID Release date HEF4017B_6 20091105 • Modifications: Section 9 “Recommended operating conditions” HEF4017B_5 20090709 HEF4017B_4 20081209 HEF4017B_CNV_3 19950101 HEF4017B_CNV_2 19950101 HEF4017B_6 Product data sheet Data sheet status Change notice Product data sheet - Product data sheet ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Application information Package outline ...

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