74LVC169BQ,115 NXP Semiconductors, 74LVC169BQ,115 Datasheet - Page 2

• Manufacturer Part Number: 74LVC169BQ,115
• Description: IC SYNC 4BIT BIN COUNT 16DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC169BQ,115

• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Logic Type: Binary Counter
• Direction: Up, Down
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Timing: Synchronous
• Count Rate: 150MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC169BQ-G; 74LVC169BQ-G; 935275616115

NXP Semiconductors
2. Features
3. Ordering information
Table 1.
74LVC169_5
Product data sheet
Type number Temperature range Package
74LVC169D
74LVC169DB
74LVC169PW
74LVC169BQ
Ordering information
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be
HIGH. The pin U/D input determines the direction of the counting. The terminal count
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,
when a counter reaches 15 in the count up mode.The pin TC output state is not a function
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For
this reason the use of pin TC as a clock signal is not recommended; see the following
logic equations:
I
I
I
I
I
I
I
I
I
I
I
I
count enable
count up: TC
count down: TC
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Up/down counting
Two count enable inputs for n-bit cascading
Built-in look-ahead carry capability
Presettable for programmable operation
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C.
N
N
HBM JESD22-A114D exceeds 2000 V
CDM JESD22-C101C exceeds 1000 V
Name
SO16
SSOP16
TSSOP16
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
=
=
CEP CET PE
Q3 Q2 Q1 Q0 CET U D
=
Q3 Q2 Q1 Q0 CET U D
Rev. 05 — 8 June 2009
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
quad flat package; no leads; 16 terminals;
body 2.5
Presettable synchronous 4-bit up/down binary counter
3.5
0.85 mm
74LVC169
© NXP B.V. 2009. All rights reserved.
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
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