74HCT4017BQ,115 NXP Semiconductors, 74HCT4017BQ,115 Datasheet - Page 15

• Manufacturer Part Number: 74HCT4017BQ,115
• Description: IC JOHNSON DECADE CNTR 16-DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT4017BQ,115

• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 10
• Reset: Asynchronous
• Count Rate: 67MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Decade
• Counting Sequence: Up
• Number Of Circuits: 1
• Logic Family: HCT
• Propagation Delay Time: 50 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Function: Counter/Divider
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74HCT4017BQ-G; 74HCT4017BQ-G; 935285358115

NXP Semiconductors
74HC_HCT4017_3
Product data sheet
Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0
when CP1 is LOW, as this would cause an extra count.
Figure 13
74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset,
the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output
pulse widths can be enlarged by inserting an RC network at the MR input.
Fig 12. Counter expansion
Fig 13. Divide-by 2 through divide-by 10
clock
shows an example of a divide-by 2 through divide-by 10 circuit using one
CP0
CP1
Q0 Q1
9 decoded
74HCT4017
first stage
74HC4017
outputs
divide - by 5
divide - by 2
divide - by 6
divide - by 7
divide - by 3
- - - -
MR
Rev. 03 — 8 January 2008
Q8 Q9
Johnson decade counter with 10 decoded outputs
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
74HCT4017
74HC4017
74HC4017; 74HCT4017
CP0
CP1
intermediate stages
Q0 Q1
74HCT4017
74HC4017
8 decoded
outputs
- - - -
MR
Q5-9
CP0
CP1
V
MR
Q9
Q4
Q8
CC
Q8 Q9
V
fin
divide - by 10
divide - by 9
divide - by 4
divide - by 8
fout
CC
001aah249
CP0
CP1
Q1
© NXP B.V. 2008. All rights reserved.
8 decoded
74HCT4017
last stage
74HC4017
outputs
- - - - - -
MR
Q8 Q9
001aah248
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