ST16-19RFRDCS ST Microelectronics, ST16-19RFRDCS Datasheet - Page 14

• Manufacturer Part Number: ST16-19RFRDCS
• Description: CHIP SET INTERFACE SPECIFICATION
• Manufacturer: ST Microelectronics

ST16-19RFRDCS
1.6.2 Status register
The mapping of the different state bits is given by the following table:
Table 3 : Reception status register description
1.7 FPGA PIN-OUT & CHIP SET BLOCK DIAGRAM
The FPGA pin-out is given by the list below:
Table 4 : FPGA pin out
8/15
clk1356
mic_ctrl_ndata
mic_data<0>
mic_data<1>
mic_data<2>
mic_data<3>
mic_data<4>
mic_data<5>
mic_data<6>
mic_data<7>
mic_r_nw
mic_strb_b
reset
rx_bpsk_in
rx_fifo_empty
rx_irq_eof
rx_valid
tx_fifo_empty
tx_start
tx_streamout
"Address
’0
Signal
Reception Control
bit 5:
bit 6:
bit 7:
bit [1:0]:
bit 2:
bit 3:
bit 4:
Rx_Bad_StopBit
P2
P176
P184
P185
P186
P187
P188
P189
P190
P191
P181
P179
P102
P48
P89
P180
P198
P29
P30
P37
Rx_Speed_Value
Rx_CRC_OK
Rx_EGT_TooLong
ST Reserved => read at '0'
ST Reserved => read at '0'
ST Reserved => read at '0'
Site
"00" = 106K
’0’ = CRC OK
‘0' = Stop Bit Value OK '1' = Stop Bit wrong => frame wrong?
‘0' = EGT OK
"Description
"01" = 212K
’1’ = CRC Wrong
'1' = EGT too long
FSD_CHIPSET_B/0104VP2
"10" & "11"= 424K