ST16-19RFRDCS ST Microelectronics, ST16-19RFRDCS Datasheet - Page 9

• Manufacturer Part Number: ST16-19RFRDCS
• Description: CHIP SET INTERFACE SPECIFICATION
• Manufacturer: ST Microelectronics

FSD_CHIPSET_B/0104VP2
1.3.3 Write access chronogram
FPGA write access chronogram, for transmission FIFO or control register:
Figure 1 : FPGA write access chronogram
In figure1, two types of access are shown. The first one is a Control register access (Mic_Ctrl_Data = ’1’)
and the second one is a FIFO access (Mic_Ctrl_Data = ’0’).
1.3.4 Read access chronogram
FPGA read access chronogram, for reception FIFO or status register:
Figure 2 FPGA read acces chronogram
In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that
the data can be recuperated.
Mic_Ctrl_Data
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Tx_start
Mic_RW
Mic_Strb_b
Tx_fifo_empty
Mic_Ctrl_Data
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Mic_RW
Mic_Strb_b
Tx_start
Tx_fifo_empty
t0
t1
Acquisition of the first byte
t5
t1
t3
Control register writing
t3
t6
t2
t4
t2
t4
Acquisition of the next bytes,
except the last one
Data writing
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