CS98000-CQ Cirrus Logic, Inc., CS98000-CQ Datasheet
CS98000-CQ
Related parts for CS98000-CQ
CS98000-CQ Summary of contents
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... Future Firmware Enhancements: • Web I/O via AC-Link Input & Built-in Soft Modem • DVD Audio Navigation • MLP Decoder, DTS Decoder, AAC Decoder • MP-3 Encoder, Ripping Controller ORDERING INFORMATION CS98000-CQ CS98010-CQ Memory Controller RISC-2 I-Cache D-Cache SDRAM Control MAC MMU FLASH Control ...
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... Video Interface ...................................................................................................... 7 CS98000 WITH VIDEO ENCODER.......................................................................................... 7 1.2 DC Electrical Specification ................................................................................................. 8 ABSOLUTE MAXIMUM RATING.............................................................................................. 8 ELECTRICAL CHARACTERISTICS......................................................................................... 8 2. TYPICAL APPLICATION .......................................................................................................... 9 3. FUNCTIONAL DESCRIPTION ............................................................................................... 10 3.1 Block Diagram .................................................................................................................. 10 3.2 CS98000 Device Details .................................................................................................. 10 3.2.1 RISC-32 .............................................................................................................. 10 3.2.2 DSP-32 ................................................................................................................ 10 3.2.3 System Controls .................................................................................................. 10 3.2.4 Memory Controller ............................................................................................... 11 3.2.5 Data Flow Engine ................................................................................................ 11 3.2.6 MPEG Video Decoder ......................................................................................... 11 3.2.7 System Synchronization ...................................................................................... 11 3.2.8 Audio Interface .................................................................................................... 11 3 ...
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... CS98000 with video Encoder ......................................................................................................... 7 Absolute maximum rating ............................................................................................................... 8 Electrical Characteristics ................................................................................................................ 8 Table 1. Host Port Memory Map ................................................................................................... 15 Table 2. Internal IO space map..................................................................................................... 15 Table 3. CS98000 Register Map and Blocks ................................................................................ 16 Table 4. CS98000 Registers ......................................................................................................... 16 Table 5. Pin Type legend .............................................................................................................. 25 Table 6. Pin assignments.............................................................................................................. 26 Table 7. Miscellaneous Interface Pins .......................................................................................... 31 Table 8. SDRAM Interface ............................................................................................................ 32 Table 9 ...
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... CHARACTERISTICS AND SPECIFICATIONS 1.1 AC Electrical Specifications 1.1.1 ATAPI Interface CS98000 can interface with ATAPI-type slave loader gluelessly. Figure 1 illustrates a read ATAPI trans- action and a write ATAPI transaction. PIO mode 4 is implemented for sufficient data transfer rate between ATAPI device and CS98000. ATAPI TRANSACTION Symbol ...
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... SDRAM Interface CS98000 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 2 shows the refresh cycle performed by CS98000. Figure 3 shows a burst read (length = 8) transaction, while Figure 4 shows a burst write (length = 8) transaction. Figure 5 and the following table show detailed timing. In both Figure 3 and 4, CAS latency is programmed to 3 ...
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... Output Hold Time tmdow Clk to Data Bus Valid tmsuw Data Valid to Clk 6 t mco CLOCK MRAS,MCAS MWE,AP,DQM0-3 MCKE,MA-011 DQ0-DQ31(WRITE) DQ0-DQ31(READ) t msur Figure 5. SDRAM Timing Description CS98000 mper cch ccl t mhw t mdow t t mhr msuw Min Typ Max 3 ...
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... Video Interface Figure 6 illustrates the CS98000 interfaces with standard video encoder. CS98000 WITH VIDEO ENCODER Symbol Tdsu Video data setup time Tdh Video data hold time Tsysu HSYNC or VSYNC to Clock setup time Tsyh Clock to HSYNC or VSYNC hold time Tckl Video clock low time ...
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... Normal Operating buffer rating buffer rating OUT OUT C BID CS98000 Min Max Unit -0,5 4.6 Volts -0.5 3.6 Volts -0.5 5.5 Volts - - 260 220 C o -40 125 ...
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... TYPICAL APPLICATION The Figure 7 shows a typical example of a complete internet-DVD solution using the CS98000. Remote Keyboard/ Control Front Panel Audio-L Audio ADC Audio-R Video Video Decoder DVD Loader (I/O Chan) or Loader ATAPI + Hard Drive* * Hard drive useable with ATAPI loader DS525PP1 DAA ...
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... FUNCTIONAL DESCRIPTION 3.1 Block Diagram The CS98000 block is shown in Figure 8. 3.2 CS98000 Device Details 3.2.1 RISC-32 • Powerful 32-bit RISC processor • Virtual memory support • Optimizing C compiler and source level debug- ger • Big or little endian data formats support • MAC multiply/accumulate in 2 cycles with C support. • ...
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... It supports 3 separate regions and 16 transparency overlay levels • Picture-in-picture module includes horizontal and vertical downscaling. Supports program- mable output sizes, positions, and borders • Overlay mixer with RGB to YUV conversion and output formatting CS98000 11 ...
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... There are other instructions that are de- signed to help with performing MPEG1/2 decod- ing. The CS98000 fully supports many Real Time Operating Systems (RTOS) such as WindRiver OS and ATI. The RISC processor co-ordinates on- chip multi-threaded tasks, as well as system activi- ties such as remote control and front panel control. ...
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... FIFO in DRAM. The same interface pins can be optionally config- ured as a generic 16-bit host master port. In this mode, the CS98000 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects) ...
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... The soft modem processing is handled by one of the RISC processors, which is typically dedicated for that function. Data rates (V.90 pro- tocol) are supported. The CS98000 interfaces to a simple external CODEC/DAA circuit using a flex- ible serial interface. The serial interface is a fully ...
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... MEMORY MAP 4.1 Processor Memory Map The CS98000 externally supports Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table lists the memory map as viewed by the RISC proces- sors, and identifies whether each segment is mapped or cacheable. Processor byte address 0000_0000 – 07FF_FFFF 8000_0000 - 81FF_FFFF 9400_0000 – 9CFF_FFFF 9C00_0000 – ...
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... R/W 028 R/W 02C R/W 030 R/W 034 R/W 038 R/W 16 Table 4 lists all the registers for the CS98000 and their addresses, and indicates whether the registers are read/write (R/W), read only (RO) or write only (WO). General Host DRC DMA DVD Interface Serial Interface DSP Sync Control MPEG Video Decoder ...
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... General GenIODVD_Tri_State_Enable General GenIOHST_Read_Data General GenIOHST_Write_Data General GenIOHST_Tri_State_Enable General I2C_Mstr_Read_Comand General I2C_Mstr_Write_1Byte General I2C_Mstr_Write_2Bytes General I2C_Mstr_Control General I2C_Mstr_Status General I2C_Mstr_Read_Data General RSK0_Interrupt_Mask General RSK0_Interrupt_Set General RSK0_Interrupt_Status General RSK0_Interrupt_Cause General DSP_Interrupt_Mask General DSP_Interrupt_Set General DSP_Interrupt_Status General DSP_Interrupt_Cause Table 4. CS98000 Registers (Continued) CS98000 17 ...
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... IR_Dram_Start_Address General IR_Dram_End_Address General IR_Dram_Write_Address General PLL_Control_Register1 General Low_Power_Clock_Control General PLL_Control_Register2 General PLL_Control_Register3 General PLL_Turn_Off General PLL_Clock_Divider Host Device_1_Control Host Device_2_Control Host Device_3_Control Host Device_4_Control Host Write_Data_Port Host Read_Data_Port Host Host_Start_Address Host Dram Start Address Table 4. CS98000 Registers (Continued) CS98000 DS525PP1 ...
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... DMA Fifo_End_Wr_Addr DMA Lines_and_Skip DMA Byte_Mask_Pattern CD/DVD DVD1 _Control CD/DVD DVD1 _Fifo_Base_Address CD/DVD DVD1_Fifo_Size CD/DVD DVD1_Sector CD/DVD DVD1_Start_of_Sector CD/DVD DVD1_Current_Dram_Address CD/DVD CD_Control CD/DVD CD_Error_Status CD/DVD DVD1_Status SER/DCI DCI_Control_Reg SER/DCI DCI_Status SER/DCI DCI_Dram_Rd_Start_Addr SER/DCI DCI_Dram_Wr_Start_Addr SER/DCI DCI_Nbytes_Sent Table 4. CS98000 Registers (Continued) CS98000 19 ...
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... Sync Control Frame_Period Sync Control STC_Interval Sync Control System_Time_Clock Sync Control Top_Bits Sync Control Video_PTS_FIFO_Start_Address Sync Control Video_PTS_FIFO_End_Address Sync Control Video_PTS_FIFO_Write_Address Sync Control Video_PTS_FIFO_Read_Address Sync Control Subpicture_PTS_FIFO_Start_Address Sync Control Subpicture_PTS_FIFO_End_Address Sync Control Subpicture_PTS_FIFO_Write_Address Sync Control Subpicture_PTS_FIFO_Read_Address Table 4. CS98000 Registers (Continued) CS98000 DS525PP1 ...
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... MPEG Vid Decoder MPEG_I_Base_Register MPEG Vid Decoder MPEG_P_Base_Register MPEG Vid Decoder MPEG_Dest_Control MPEG Vid Decoder MPEG_Software_Flags MPEG Vid Decoder MPEG_V_Offset MPEG Vid Decoder MPEG_AntiTearWindow MPEG Vid Decoder MPEG_Error_Pos VIS VIS_Control VIS VIS_StartX VIS VIS_EndX VIS VIS_StartY Table 4. CS98000 Registers (Continued) CS98000 21 ...
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... Video Processor Video_Line_Size Video Processor Frame_Buffer_Base Video Processor Video_Line_Mode_Buffer Video Processor Horizontal_Vertical_Filter Video Processor Source_X_Offset Video Processor Horizontal_Video_Scaling Video Processor Frame_V_Buffer_Compressed_Offset Video Processor Mb_Width Video Processor Anti-Flicker Video Processor Anti-Flicker Video Processor Anti-Flicker Video Processor Anti-Flicker Table 4. CS98000 Registers (Continued) CS98000 DS525PP1 ...
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... Subpicture Subpicture_Control Subpicture Subpicture_Display_Offset Subpicture Subpicture_Display_Scale On Screen Display OSD_Status On Screen Display OSD_Control On Screen Display OSD_Color_Number On Screen Display OSD_Color_Data On Screen Display OSD_Region1_Control On Screen Display OSD_Region1_Hlimits On Screen Display OSD_Region1_Vlimits On Screen Display OSD_Region1_DramBase On Screen Display OSD_Region2_Control On Screen Display OSD_Region2_Hlimits Table 4. CS98000 Registers (Continued) CS98000 23 ...
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... PCM PCM_In_FIFO_Start_Address PCM PCM_In_FIFO_End_Address PCM PCM_In_FIFO_Interrupt_Address PCM PCM_Out_FIFO_Interrupt_Address2 PCM PCM_Out_FIFO_Interrupt_Address3 PCM PCM_In_FIFO_Current_Address PCM SPDIF_Output_Control PCM SPDIF_Output_FIFO_Start_Address PCM SPDIF_Output _FIFO_End_Address PCM SPDIF_Output _FIFO_Current_Address PCM SPDIF_Output _FIFO_Interrupt_Address PCM SPDIF_Output_Add_Block RSK0 RISC 0 Processor registers RSK1 RISC 1 Processor registers Table 4. CS98000 Registers (Continued) CS98000 DS525PP1 ...
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... Bi-direction – 8mA drive, with pull-up Bi-direction – 4mA drive, with schmitt trigger Bi-direction – 4mA drive, with pull-up and schmitt trigger +2.5V or +3.3V power supply voltage Power supply ground Low active Low active Table 5. Pin Type legend CS98000 M_A_[11:0] M_BS_L M_D_[31:0] M_DQM_[3:0] M_RAS_L Memory IF M_CAS_L ...
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... Pin Assignments Table 6 lists the pin number, pin name and pin type for the 208 pin CS98000 package. The primary function and pin direction is shown for all signal Pin Name Type 1 VDD_PLL Pwr 2 M_A_11 O8 3 M_A_10 O8 4 GPIO_D18 B4U 5 M_A_9 O8 6 M_A_8 ...
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... SDRAM Data[23] B GenioDVD[10] B SDRAM Data[22] B SDRAM Data[26] B SDRAM Data[21] B GenioDVD[9] B SDRAM Data[27] B SDRAM Data[20] B SDRAM Data[28] B Table 6. Pin assignments (Continued) CS98000 ROM/NVRAM Data[7] B ROM/NVRAM Data[9] B ROM/NVRAM Data[6] B ROM/NVRAM Data[10] B ROM/NVRAM Data[5] B ROM/NVRAM Data[11] B ROM/NVRAM Data[4] B ROM/NVRAM Data[12] B ROM/NVRAM Data[3] B ROM/NVRAM Data[13] ...
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... Host Data[15] B Host Data[14] B Host Chip Select[3] O Host Data[13] B Host Data[12] B Host Data[11] B Host Chip Select[2] O Host Data[10] B Table 6. Pin assignments (Continued) CS98000 ROM/NVRAM Address[15] O ROM/NVRAM Address[14] O GenioMis[8] B ROM/NVRAM Decode Low O GenioHst[13] B ROM/NVRAM Address[13] O ROM/NVRAM Decode High O ROM/NVRAM Address[12] O DVD Data Strobe ...
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... Serial CODEC Bit Clock I Serial CODEC Sync B GenioMis[26] B GenioDvd[15] GenioDvd[14] GenioDvd[13] Video Input Vsync I Video Output Clock O GenioDvd[12] PLL Power 2.5V PLL Ground Table 6. Pin assignments (Continued) CS98000 DVD Control Ready I DVD Control Clock O GenioHst[19] B DVD Data[7] I DVD Data[6] I DVD Data[5] I GenioMis[3] B DVD Data[4] I ...
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... Video Input Data[5] I General Purpose IO[8] B Audio 256x/384x Clock B General Purpose IO[10] B Video Input Data[6] I General Purpose IO[11] B General Purpose IO[12] B General Purpose IO[13] B General Purpose IO[14] B Video Input Data[7] I Table 6. Pin assignments (Continued) CS98000 GenioMis[4] B GenioMis[24] B GenioMis[5] B GenioMis[16] B GenioMis[17] B Audio PLL Input Bypass I GenioMis[18] B General Purpose IO[1] B GenioMis[19] B GenioMis[20] B ...
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... SDRAM Interface These pins are used to interface the CS98000 with some external SDRAM. The CS98000 can interface with SDRAM of various size. Both 16 and 32 bit data width is supported, but best performance is achieved with 32 bits ...
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... NVM_WE_L 62 NVM_OE_L 32 Type B Memory Data Bus. CS98000 can use all 32 bits or can use only M_D[15..0], in which case M_D[31..16] can be left un-con- nected. O Memory Address Bus. Connect in order starting with M_A[0] to all RAM address pins not already connected to M_BS_L or M_AP. Unused upper M_A pins unconnected. ...
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... Video Output Interface This is the interface to a video encoder chip that will send the CS98000 video signals to a TV. The output format is either CCIR-601 or CCIR-656. The CS98000 supports both master and slave con- figuration. For CCIR-656 mode, the CS98000 must Pin Signal Name ...
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... O Audio Serial Data Out[3]. O S/PDIF Output I Audio Input Bit Clock. The CS98000 can be programmed to use the Audio Output function’s internally generated bit clock, in which case this pin is not required. I Audio Input Left/Right Clock. The CS98000 can be pro- grammed to use the Audio Output function’s internally gen- erated LR clock, in which case this pin is not required ...
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... Host Master/ATAPI Interface This 16 bits parallel host interface allows the CS98000 host master, controlling other de- vices that would be used on the same system. The interface supports a programmable protocols and speeds, including multiplexed and non-multiplexed addressing. Slaves with different protocols can be connected at the same time, controlled by different chip selects ...
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... DVD data clock from loader Table 15. DVD I/O Channel Interface Type B 21 General purpose I/O’ General purpose I/O’s B General purpose I General purpose I/O’ General purpose I/O’ General purpose I/O’s B General purpose I/O Table 16. General Purpose I/O Interface CS98000 Description Description DS525PP1 ...
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... VSS_CORE 126, 138, 158, 176, 200 18, 35, 58, 96, VSS_IO 119, 143, 182 DS525PP1 Type 2.5V for internal PLLs 2.5V for internal core logic 3.3V for I/O’s Ground for internal PLLs Ground for internal core logic Ground for I/O’s Table 17. Power and Ground CS98000 Description 37 ...
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... PACKAGE SPECIFICATIONS 208 0.50 0.20 38 30.6 28.00 157 156 105 104 0. WITH PLATING BASE METAL DETAIL A CS98000 3.80(MAX) 3.35 0.35 Detail A 0 (MIN) R0.15 0.2 (MIN) R0.20 0.50 0.1 5 1.3 0.1 DS525PP1 ...
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Notes • ...
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