STD0550 ST Microelectronics, Inc., STD0550 Datasheet - Page 7

• Manufacturer Part Number: STD0550
• Description: Matrix Display Digital TV Processor
• Manufacturer: ST Microelectronics, Inc.

General Description
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In global mute mode, the incoming bit-stream is decoded normally but the PCM and S/PDIF
outputs are soft-muted. This mode is used to prepare a period of the decoding mode, in order to
synchronize audio and video data without hearing the audio.
Analog Audio Sources are demodulated using external IC STV82x7. Demodulated digital audio is
sent to STV82x7 which also includes Audio processing: virtualizers (SRS TruSurround XT which is
Virtual Dolby Digital and Virtual Dolby Surround compliant) and sound enhancements (spatial
effects, bass enhancements, dialog enhancement).
Modem analog front-end interface
The modem analog front-end interface is used to transfer transmit and receive DAC and ADC
samples between the memory and an external modem analog front-end (MAFE), using a
synchronous serial protocol. DMA is used to transfer the sample data between memory buffers
and the MAFE interface module, with separate transmit and receive buffers and double buffering
of the buffer pointers. FIFOs are used to take into account the access latency to memory, in a
worst case system and to allow the use of bursts for memory bandwidth efficiency improvement.
V22bis is supported by software.
Slave CPU Memory subsystem
On-chip
The on-chip memory includes 2 Kbytes of instruction cache, 2 Kbytes of data cache and
4 Kbytes of SRAM. The subsystem provides 240 Mbytes of internal bandwidth, supporting
pipelined 2-cycle internal memory access.
The instruction and data caches are direct-mapped, with a write-back system for the data-cache.
The caches support burst accesses to the external memories for refill and write-back.
Off-chip
There are two off-chip memory interfaces:
The EMI uses minimal external support logic for the memory subsystems. It accesses a
32-Mbyte physical address space (greater if SDRAM is used) in four general purpose memory
banks of 8 or 16 bits wide, 21 or 22 address lines, and byte select. For applications requiring
extra memory, the EMI supports this extra memory with zero external support logic, even for 16-
bit SDRAM devices. The EMI can be configured for a wide variety of timing and decode functions
by the configuration registers. The timing of each of the four memory banks can be set
separately, with different device types being placed in each bank with no need for external
hardware.
Serial communication
Asynchronous serial controllers
The asynchronous serial controller (ASC), also referred to as the UART interface, provides serial
communication between the STD0550 and other microcontrollers, microprocessors or external
peripherals. The STD0550 has three ASCs available for applications. An additional UART
interface is used for the communication between the master CPU and the slave CPU.
MPEG memory interface controls the movement of data between the STD0550 and 16, 32,
64 or 128 Mbits of SDRAM. This external SDRAM stores the display data generated by the
MPEG decoder and the slave CPU working data.
The external memory interface (EMI2) accessed by the slave CPU is used for the transfer of
data and programs between the STD0550 and external peripherals, flash and additional
SDRAM.
STD0550