STD0550 ST Microelectronics, Inc., STD0550 Datasheet - Page 8

• Manufacturer Part Number: STD0550
• Description: Matrix Display Digital TV Processor
• Manufacturer: ST Microelectronics, Inc.

STD0550
1.2.6
1.2.7
1.2.8
1.2.9
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable.
Parity, framing, and overrun error detection increase data transfer reliability. Transmission and
reception of data can be double-buffered, or 16-deep FIFOs can be used. A mechanism to
distinguish the address from the data bytes is included for multiprocessor communication.
Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a
separate serial clock signal.
Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the
transmitter and the receiver use the same data frame format and the same baud rate. Each ASC
can be set to operate in smartcard mode for use when interfacing to a smartcard.
Synchronous serial control
The two synchronous serial controllers (SSCs) provide high-speed interface to a wide variety of
serial memories, remote control receivers and other microcontrollers. They support some
features of the serial peripheral interface bus (SPI) and the I
programmed to interface to other serial bus standards. They share pins with the parallel input/
output (PIO) ports, and support half-duplex synchronous communication. One SSC supports
full-duplex synchronous communication.
Hardware transport stream demultiplexer interface
The STD0550 can be connected to a front-end through the following interfaces:
The PIO pins can be tri-stated under software control to support low cost DVB-CI
implementations and similar module interfaces.
On-chip PLL
There are three on-chip frequency synthesizers and one PLL, accepting 27 or 54 MHz input,
which generate all the internal high-frequency clocks needed for the slave CPU, MPEG and
audio subsystems.
Diagnostic controller (DCU)
The ST20 diagnostic controller unit (DCU) is used to boot the CPU and to control and monitor the
chip systems via the standard IEEE 1194.1 test access port. The DCU includes on-chip
hardware with ICE (in-circuit emulation) and LSA (logic state analyzer) features to facilitate
verification and debugging of software running on the on-chip CPU in real time. It is an
independent hardware module with a private link from the host to support real-time diagnostics.
The slave CPU and master CPU each have their own DCU.
Interrupt subsystem, Slave CPU
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active
process so that an interrupt handling process can be run. An interrupt can be signalled by one of
the following: a signal on an external interrupt pin, a signal from an internal peripheral or
subsystem, software asserting an interrupt in the pending register.
Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level
controller. The interrupt controller supports eight prioritized interrupts as inputs and manages the
pending interrupts. This allows the nesting of preemptive interrupts for real-time system design.
Each interrupt can be programmed to be at a lower or higher priority than the high priority
process queue.
transport stream serial interface,
transport stream parallel interface.
2
C bus. The SSCs can be
General Description
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