IDT72V36110L10PF IDT, Integrated Device Technology Inc, IDT72V36110L10PF Datasheet - Page 23
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IDT72V36110L10PF
Manufacturer Part Number
IDT72V36110L10PF
Description
IC FIFO SYNC 131KX36 10NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V36110L7-5BB.pdf
(48 pages)
Specifications of IDT72V36110L10PF
Function
Synchronous
Memory Size
4.7M (131K x 36)
Data Rate
166MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
4.5Mb
Access Time (max)
6.5ns
Word Size
36b
Organization
128Kx36
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
40mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36110L10PF
800-1530
800-1530
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V36110L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V36110L10PF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT72V36110L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG ( HF )
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
If asynchronous PAE configuration is selected, the PAE is asserted LOW
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
TM
36-BIT FIFO
23
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536 for the
IDT72V36100 and 131,072 for the IDT72V36110.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72V36100 and 131,073 for the IDT72V36110.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
for 18-bit wide data or (Q
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
-Q
35
) are data outputs for 36-bit wide data, (Q
0
-Q
n
0
)
-Q
8
) are data outputs for 9-bit wide data.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
0
- Q
17
) are data outputs