74HCT40105D,118 NXP Semiconductors, 74HCT40105D,118 Datasheet - Page 19

• Manufacturer Part Number: 74HCT40105D,118
• Description: IC FIFO REGISTER 4X16 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT40105D,118

• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Other names: 74HCT40105D-T; 74HCT40105D-T; 933715220118

Philips Semiconductors
Note to Fig.22
Sequence 1 (Both FIFOs empty, starting shift-in process):
After a MR pulse has been applied FIFO
empty. The DOR flags of FIFO
to no valid data being present at the outputs. The DIR flags
are set HIGH due to the FIFOs being ready to accept data.
SO
These pulses allow two data words to ripple through to the
output stage of FIFO
When data arrives at the output of FIFO
generated (3). When SO
out and a second bit ripples through to the output after
which DOR
Sequence 2 (FIFO
After the MR pulse, a series of 16 SI pulses are applied.
When 16 words are shifted in, DIR
FIFO
empty.
Sequence 3 (FIFO
When 17 words are shifted in, DOR
valid data remaining at the output of FIFO
HIGH, being the polarity of the 17th data word (6). After the
32th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
1998 Jan 23
4-bit x 16-word FIFO register
B
Fig.22 Waveforms
is held HIGH and two SI
B
being full (5). DOR
showing the
functionally and
inter-
communication
between two
FIFOs
(refer to Fig.19).
B
goes HIGH (4).
B
A
runs full):
runs full):
A
and to the input stage of FIFO
B
A
goes LOW, the first bit is shifted
goes LOW due to FIFO
A
A
pulses are applied (1).
and FIFO
B
A
remains LOW due to
remains HIGH due to
B
, a DOR
A
A
B
and FIFO
. Q
go LOW due
nA
B
remains
pulse is
A
being
B
B
are
(2).
19
Sequence 4 (Both FIFOs full, starting shift-out process):
SI
These pulses shift out two words and thus allow empty
locations to bubble-up to the input stage of FIFO
proceed to FIFO
at the input of FIFO
a new word is shifted into FIFO
now the second empty location reaches the input stage of
FIFO
Sequence 5 (FIFO
At the start of sequence 5 FIFO
due to two words being shifted out and one word being
shifted in sequence 4. An additional series of SO
are applied. After 15 SO
shifted into FIFO
Sequence 6 (FIFO
After the next SO
input stage of FIFO
SO
empty (14). Additional SO
word remains available at the output Q
A
B
is held HIGH and two SO
pulses, DOR
A
, after which DIR
A
B
B
B
(9). When the first empty location arrives
. DOR
A
B
pulse, DIR
B
A
remains LOW due to both FIFOs being
runs empty):
runs empty):
, a DIR
being empty (13). After another 15
A
B
A
remains HIGH (11).
pulses, all words from FIFO
B
remains LOW (12).
pulses have no effect. The last
A
74HC/HCT40105
B
pulse is generated (10) and
B
pulses are applied (8).
A
remains HIGH due to the
A
. SI
contains 15 valid words
A
Product specification
is made LOW and
n
.
B
B
, and
pulses
A
are