74HCT7403D,518 NXP Semiconductors, 74HCT7403D,518 Datasheet - Page 27

IC FIFO REGISTER 64X4 3ST 16SOIC

74HCT7403D,518

Manufacturer Part Number
74HCT7403D,518
Description
IC FIFO REGISTER 64X4 3ST 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT7403D,518

Function
Asynchronous, Synchronous
Memory Size
256 (64 x 4)
Data Rate
15MHz
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Access Time
-
Other names
74HCT7403D-T
74HCT7403D-T
933999390518
Philips Semiconductors
Note to Fig.23
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFO
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SO
is held HIGH and two SI
of FIFO
When SO
HIGH (4).
September 1993
handbook, full pagewidth
4-Bit x 64-word FIFO register; 3-state
SO
DOR B OUTPUT
Q
DIR B OUTPUT
DOR A OUTPUT
Q nA OUTPUT
DIR A OUTPUT
SI
D
MR INPUT
nA
nB
A
Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18).
B
A
INPUT
INPUT
OUTPUT
and to the input stage of FIFO
INPUT
B
goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DOR
sequence 1
A
(1)
pulses are applied (1). These pulses allow two data words to ripple through to the output stage
(3)
(2)
(4)
sequence 2
B
A
(2). When data arrives at the output of FIFO
and FIFO
B
(5)
are empty. The DOR flags of FIFO
(6)
sequence 3
27
(7)
sequence 4
(8)
(9)
(10)
(11)
sequence 5
B
, a DOR
A
and FIFO
74HC/HCT7403
B
pulse is generated (3).
(12)
(13)
Product specification
B
go LOW due to no
sequence 6
MGA687
B
(14)
goes
B

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