74HCT7030D,118 NXP Semiconductors, 74HCT7030D,118 Datasheet - Page 18

• Manufacturer Part Number: 74HCT7030D,118
• Description: IC 9X64 FIFO REGISTER 3ST 28SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7030D,118

• Function: Asynchronous, Synchronous
• Memory Size: 576 (9 x 64)
• Data Rate: 33MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Other names: 74HCT7030D-T; 74HCT7030D-T; 933798900118

Philips Semiconductors
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 128 words
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, data arrives at the output of FIFO
generated. The requirements of SI
edge of DOR
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
full. After a bubble-up delay a DIR
from the output of FIFO
width of DOR
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
December 1990
9-bit x 64-word FIFO register; 3-state
The PC74HC/HCT7030 is easily cascaded to increase word capacity without any
external circuitry. In cascaded format, all necessary communications are handled
by the FIFOs. Figs 17 to 19 demonstrate the intercommunication timing between
FIFO
FIFOs, when shifted full and shifted empty again.
A
and FIFO
A
B
. After a second bubble-up delay an empty space arrives at D
and Q
B
. Fig.22 gives an overview of pulses and timing of two cascaded
nA
. After a second ripple through delay, data arrives at the output of FIFO
A
to the input of FIFO
Fig.19 Cascading for increased word capacity; 128 words
B
B
pulse is generated, which acts as a SO
and D
nB
B
are satisfied by the DOR
. The requirements of the SO
18
A
A
pulse width and the timing between the rising
9 bits.
. Due to SO
A
A
nA
pulse for FIFO
pulse for FIFO
, at which time DIR
B
pulse, when both FIFOs are initially
A
being HIGH, a DOR pulse is
9 bits.
A
A
74HC/HCT7030
. One word is transferred
is satisfied by the pulse
B
.
A
Product specification
goes HIGH.